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Visitor
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Registered: ‎03-19-2018

SGMII config through PS-GTR GEM1

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Hi everyone,

I’m currently working on a project using the Xilinx Ultrascale+ MPSoc processor. I’m working with the XCZU3EG processor, and I’m running only the R5 core.
Because of the hardware configuration on our board, we need to activate the SGMII through GEM1 to work with Ethernet.

 

In the UG1085 Technical Reference Manual, p1053, it is said that the GTGREF0_REF_CTRL is used for the reference clock of the PS-GTR.
One of our lead here is to activate the GTGREF0_REF_CTRL register in the CRF_APB module. However, this register is visible when debugging, but not on the Xilinx Register reference guide.

 

Besides, in the PG201 documentation (“ZYNQ Ultrascale+ MPSoC Processing System v3.1”) p184, the range of the Frequence for this reference clock has to be between -2 and -1, which doesn’t seems to make sense


We are using Vivado to configure the board, but we cannot see what to modify and how.

Could you help us here please ?

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Visitor
Visitor
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Registered: ‎03-19-2018

Re: SGMII config through PS-GTR GEM1

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Hi drajunad,

 

Thanks for the link. However, I'm not using the Xilinx SDK environment to flash and debug, only to generate the psu_init, so I couldn't run it.

But we found the solution. Multiple registers needed to be modified manually after Vivado export the hardware, namely :

Thank you all for your time and help

View solution in original post

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Moderator
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Registered: ‎07-31-2012

Re: SGMII config through PS-GTR GEM1

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Hi @arthur_mouf,

 

Please see if the attached Vivado configuration for PS GTR for GEM help you.

 

Regards

Praveen


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Visitor
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Registered: ‎03-19-2018

Re: SGMII config through PS-GTR GEM1

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Hi @pvenugo,

Thanks for your reply. I've checked the Vivado config, the parameters are configured as in your file.

However, I'm not booting using Linux. I do everything through the JTAG in the DDR. So I guess I'm not using this .dtsi file and I don't have this &gem1{...} config.


But maybe I can do it in another way, via a .tcl script for instance ?

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Xilinx Employee
Xilinx Employee
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Registered: ‎04-03-2018

Re: SGMII config through PS-GTR GEM1

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HI  @arthur_mouf,

 

I hope you have tried using SGMIIInit_fix.tcl script provided in AR#66592(https://www.xilinx.com/support/answers/66592.html).

Does this script solved your issue?

 

 

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Visitor
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Registered: ‎03-19-2018

Re: SGMII config through PS-GTR GEM1

Jump to solution

Hi drajunad,

 

Thanks for the link. However, I'm not using the Xilinx SDK environment to flash and debug, only to generate the psu_init, so I couldn't run it.

But we found the solution. Multiple registers needed to be modified manually after Vivado export the hardware, namely :

Thank you all for your time and help

View solution in original post