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atippic
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Registered: ‎06-04-2018

SLVERR from L3 not raised in ISR of ARM PL310 L2 cache controller

Hello,

I am trying to raise L3 SLV interrupts of the ARM PL310 L2 cache controller by generating an AXI slave error on a PL slave peripheral IP. On my Xilinx Zynq SoC, the ARM PL310 revision is r3p2.

Here is the current status:

The AXI slave error is correctly propagated from the L2C's M1 master port back to to the L2C's slave port, and then back to the CPU's AXI master port such that a data abort exception is raised.

However, the interrupt is not set in either Interrupt Pending Register (IPR) or Interrupt Status Register (ISR) of the L2C.

I did not find any required configuration of the ARM PL310's L2C to enable reporting of these interrupts... I am relying on this information to handle CPU exceptions with fine grain. So it is important for me to get these interrupts to be notified, and any help would be welcome.

Thank you.

Regards,

Florian

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