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Registered: ‎07-23-2019

SPI not working unless Force Slave Select

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I have a Zynq us+ where the PS has an SPI through EMIO. I couldn't get it to work. The device (a DAC) didn't seem to understand anything. The command is 24 bits. I noticed in the SS signal produced by the SPI there were two upgoing glitches, every 8 bits. after a couple of days of debugging things, I found that, to put it simple:

The SPI interface won't work if the SS signal is to be low for longer than 8 bits.

I fixed it by activating the Force slave Select option.

So the question is:

Is there something that can be done to have a continuous, glitch-less SS signal when sending more than 8 bits in a row? Or is the Force Select the only way?

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Registered: ‎04-13-2015

@archangel-lightworks , from your description, yes the force select is the only way.  Not using force select means the SPI module is in "automatic select" and the SS signal will go up whenever the TX FIFO is empty. If you don't want to to control the SS, then you'll have to rework your code to make sure to fill the TX FIFO as fast as possible... as soon as the FIFO is empty the SS will go up.

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Registered: ‎04-13-2015

@archangel-lightworks , from your description, yes the force select is the only way.  Not using force select means the SPI module is in "automatic select" and the SS signal will go up whenever the TX FIFO is empty. If you don't want to to control the SS, then you'll have to rework your code to make sure to fill the TX FIFO as fast as possible... as soon as the FIFO is empty the SS will go up.

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Registered: ‎07-23-2019

 

I expected some way to specify how many bits are in a word. I could try filling the buffer but if the sw fails to keep it busy I'll be in trouble, so it's done that way, it works "don't touch it" :D

 

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