I am using xc7z030-ffg676-2 and Vivado 2013.4. We are using two GMII Ethernets through EMIO. GMII RX clocks inputs are connected to SRCC clock pin (MRCC pins are used for TX clock input). Clocks are single-ended so only P side of SRCC/MRCC clocks are used.
Is there problem using SRCC clock input for GMII RX clock via EMIO? Should it be MRCC when this clock is routed to PS side GEM via EMIO? Vivado does not generate any errors using SRCC for that. Actually when RX clock is routed directly to EMIO do I have to use SRCC/MRCC pin at all?