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Contributor
Contributor
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Registered: ‎09-24-2016

SWDT documentation unclear: External reset without internal reset?

The Zynq 7000 series system watchdog (SWDT) documentation on the zero-mode register (XWDTPS_ZMR_OFFSET) suggests that internal and external signals/resets can be invidivually enabled/disabled.

 

bit #0 (WDEN) Watchdog enable - if set, the watchdog is enabled and can generate any signals that are enabled.

bit #1 (RSTEN) Reset enable - if set, the watchdog will issue an internal reset when the counter reaches zero, if WDEN = 1.

 

I am concerned about the description of bit #0: "if set, the watchdog is enabled and can generate any signals that are enabled."

 

However, that seems not true; as I have enabled SWDT_RST_OUT on MIO pin 39 and WDEN=1 but I do not see this signal generated UNLESS I also enable bit #1 (RSTEN).

 

Figure 8.2 suggests that SWDT reset and SWDT_RST_OUT / MIO reset are tied together.

 

Can someone confirm or clarify this?

 

Regards,

 

Leon.

 

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