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johnfuhrer
Visitor
Visitor
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Registered: ‎06-05-2009

Signal generator with AXI streaming DMA from DDR2

My setup consists of an AXI uBlaze EDK design on a Virtex 6 custom board. We have a DDR2 on the board with digital data that we send to a DAC using DMA to AXI streaming. All works fine except from the following problem we have:

 

We want to send data constantly, that is, we have a ring of Buffer Descriptors that we would like to have sending data all the time in a loop non-stop as the digital data is a period of a periodic signal. So far we can only get them to send once, that is one full cycle of the ring and then the uBlaze processor has to find out that the cycle is complete (or do it with interrupts),  re-set all the BDs and access the tail descriptor.

 

This takes up too much processing time. The question is, is there any way to set up the ring of BDs so that it automatically keeps sending data in a loop without intervention from the uBlaze processor?

 

(NOTE: I have already read a good number of datasheets and other documents but haven't found out)

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wweimermed
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Registered: ‎06-23-2009

As far as I know there is no way to do this in HW, but I think you should be able to solve this with the uBlaze if you structure things a little differently. Depending on the data rates involved, you will have to set up the BD rings so that you have enough BDs and each BD describes a large transfer- maybe 1Kbyte for example. You then need to configure interrupts so that after let's say 25% of your BDs have been used, you get an interrupt. You then recycle the BDs and add them to the tail of the BDring. This way you never have an empty BD ring. The main point is to give the uBlaze enough time to repopulate the BDring after the interrupt occurrs. This is a trade-off between number of BDs, transfer size per BD, and when then interrupts are set to occur.

 

 

 

 

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