cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jmonteiro-dme
Explorer
Explorer
10,381 Views
Registered: ‎05-15-2009

Simple question: Update custom core in XPS

Jump to solution

Hi,

After adding an IPcore to the microblaze architecture using XPS, if i want to change user_logic of this same core do I need to add the IP core again and remove the previous one, or can I simply re-import it?

 

Best,

JM

Message Edited by jmonteiro-dme on 05-27-2009 05:51 AM
Message Edited by jmonteiro-dme on 05-27-2009 05:51 AM
0 Kudos
1 Solution

Accepted Solutions
xiaofeip
Xilinx Employee
Xilinx Employee
12,892 Views
Registered: ‎08-07-2007

Hi JM,

 

I just realized that you are using ISE. I'm not sure if ProjNav can handle this. anyway, the key is to make sure that PlatGen is re-run.

 

-XF

View solution in original post

0 Kudos
8 Replies
bassman59
Historian
Historian
10,364 Views
Registered: ‎02-25-2008

jmonteiro-dme wrote:

Hi,

After adding an IPcore to the microblaze architecture using XPS, if i want to change user_logic of this same core do I need to add the IP core again and remove the previous one, or can I simply re-import it?

 



I never use the import wizard, but when you make changes to the core when it is instantiated in your EDK system, you don't need to re-import it. You might need to completely clean the design.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
xiaofeip
Xilinx Employee
Xilinx Employee
10,359 Views
Registered: ‎08-07-2007

IMO, the only purpose of using the Import Wizard is to help you update MPD and PAO, etc. files, after you modified the hdl code.

 

You can simply modily  those files manually if you understand the sysntax.

 

And if you set the option ARCH_SUPPORT_MAP in MPD to DEVELOPMENT, you don't even have to clean the design. Every time you run platgen, it will be resynthesized. 

 

-XF

0 Kudos
jmonteiro-dme
Explorer
Explorer
10,326 Views
Registered: ‎05-15-2009

Thank you very much for your answers.

 

In the core's MPD I have

 

OPTION ARCH_SUPPORT_MAP = (OTHERS=DEVELOPMENT),

 

And when I make a change in the core's VHD i'm simply doing "update bitstream with processor data" in ISE. Will it resynthesize the performed changes in the core's user_logic, even without cleaning the EDK project files?

 

Best,

JM

 

 

0 Kudos
xiaofeip
Xilinx Employee
Xilinx Employee
10,324 Views
Registered: ‎08-07-2007

Hi JM,

 

That's the expected behavior. I'll also "rescan" the repository after the modification, just in case there're also modifications with the mpd file.

 

-XF

0 Kudos
jmonteiro-dme
Explorer
Explorer
10,319 Views
Registered: ‎05-15-2009

Thank you XF,

 

Sorry for asking this, but how do I rescan the files?

 

Best,

JM

0 Kudos
xiaofeip
Xilinx Employee
Xilinx Employee
10,316 Views
Registered: ‎08-07-2007

Hi JM,

 

Go to Project menu and you will see it. Or just find the rescan button on the toolbar.

 

-XF

0 Kudos
xiaofeip
Xilinx Employee
Xilinx Employee
12,893 Views
Registered: ‎08-07-2007

Hi JM,

 

I just realized that you are using ISE. I'm not sure if ProjNav can handle this. anyway, the key is to make sure that PlatGen is re-run.

 

-XF

View solution in original post

0 Kudos
jmonteiro-dme
Explorer
Explorer
10,309 Views
Registered: ‎05-15-2009

I don't think it happens that way, hence my doubt: If, for instance, I update the user_logic to possess an error, say put "errorblablabla?!?!" in the middle of the vhd, and if i "update the bitstream with processor data" in ISE, it will not detect the vhd error. I rescaned project files..

 

Best,

JM

0 Kudos