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cseamans
Observer
Observer
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Registered: ‎11-05-2019

Simulating Custom AXI Slave Peripheral

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Hi,

I created a custom AXI4 slave peripheral and added some code to put the written data in corresponding registers. However I cannot verify/simulate it with the AXI Verification IP. I generated the AXI Verification IP example project and replaced the auto-generated AXI Slave component in the block design with my own custom AXI4 slave peripheral (packaged as an IP).

When I run simulation, the following errors occur:

WARNING: [VRFC 10-4940] 'ex_sim_pcie_regs_intake2_v1_0_0' remains a black box since it has no binding entity [/home/cameron/Documents/Examples/axi_vip_1_ex/axi_vip_1_ex.ip_user_files/bd/ex_sim/sim/ex_sim.vhd:284]

ERROR: [VRFC 10-2991] 'IF' is not declared under prefix 'inst' [../../../../imports/axi_vip_1_slv_stimulus.sv:47]

So I changed line 47 in axi_vip_1_slv_stimulus.sv from

'agent = new("slave vip agent",DUT.ex_design.axi_vip_slv.inst.IF);'  to

'agent = new("slave vip agent",DUT.ex_design.pcie_regs_intake2_v1_0);'. But this resulted in the following error

'ERROR: [XSIM 43-3138] "../../../../imports/axi_vip_1_slv_stimulus.sv" Line 47. Cross Language Hierarchical name(DUT.ex_design.pcie_regs_intake2_v1_0) is not supported in this context. '.

Is there a better way to simulate/verify my custom AXI4 peripheral than to use the AXI VIP example design? If not, how do I successfully put my custom AXI4 IP into the example verification project? I've attached my block design and the VHDL for the custom AXI4 slave peripheral.

AXI4 Slave Verification BlockDesign.PNG
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florentw
Moderator
Moderator
666 Views
Registered: ‎11-09-2015

HI @cseamans 

The blog articles @dgisselq is mentioning are the AXI Basic Series I wrote.

There is one obvious issue in your code. You are declaring a slave agent but you do not have a slave AXI VIP...only a master and a path-through.

So just remove the line of code.

Really what you should do is try to understand the example project first and code before trying to use it on your side.

The example I wrote below is simpler and explained. Take time to go through it:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-3-Master-AXI4-Lite-simulation-with-the-AXI-VIP/ba-p/1058302


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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3 Replies
dgisselq
Scholar
Scholar
680 Views
Registered: ‎05-21-2015

@cseamans,

While I'm not quite certain how to get Xilinx's AXI VIP up and running, I thought you should know that the VHDL design you are copying from is broken and Xilinx's VIP isn't known for revealing the bugs within it.  You can read a full test report of the problem here.  The IP packager generated design has been known over the years to offer the appearance of working, while randomly and seemingly inexplicably locking up the entire AXI bus and the design that depends upon it with it.

Have you seen the blog articles from earlier this year on how to set up the AXI VIP for your current attempted purpose?

Dan

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florentw
Moderator
Moderator
667 Views
Registered: ‎11-09-2015

HI @cseamans 

The blog articles @dgisselq is mentioning are the AXI Basic Series I wrote.

There is one obvious issue in your code. You are declaring a slave agent but you do not have a slave AXI VIP...only a master and a path-through.

So just remove the line of code.

Really what you should do is try to understand the example project first and code before trying to use it on your side.

The example I wrote below is simpler and explained. Take time to go through it:

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/AXI-Basics-3-Master-AXI4-Lite-simulation-with-the-AXI-VIP/ba-p/1058302


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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cseamans
Observer
Observer
582 Views
Registered: ‎11-05-2019

Thank you @florentw and @dgisselq for your replies. I've had to move my attention to other projects for the time being, but I will look back into this soon!

Thanks

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