SmartConnect Failing Timing

[achafe]

I am attempting to implement multiple Xilinx MIPI DSI cores on an Artix 7 and use the Smartconnect to interface with all of the AXI-Lite inputs. MIPI requires the AXI-Lite interface to run at 200Mhz but i am unable to get the SmartConnect to pass timing at this clock speed. I have attempted to modify the Advanced Properties to add extra pipelining registers in the failing paths, however whenever i do this the changes are reverted as soon as I revalidate the block diagram, and any attempt at building produces the same timing results. How can i clean up the SmartConnect timing? 

[demarco · Accepted solution]

Hi @achafe ,

Which version of the tools are you using? If it is before 2019.1, I recommend using AXI Interconnect to connect to AXI-Lite interfaces.

Starting in 2019.1, SmartConnect has undergone a lot of improvements to make it more timing and area comparable to AXI Interconnect. Before that, it was pretty inefficient.

Regards,

Deanna

[achafe]

Thank you! I will try that!

Amy