Our EDK project includes GbE, DDR2, Parallel Flash and other sub modules. The EDK project is used as a sub module of an ISE project. The place and route could not meet all the timing requirement, having a timing score less than 2000ps usually only involving a few signals in the 5ns clock domain which is for the DDR2. We contacted Xilinx Tech Support and they cannot help us in reducing the timing score down to zero. Albeit, we ran the project on the real hardware and it worked reliably.
Recently we noticed that after making some small changes to the ISE project, the software may failed to boot. And another small change may bring it back to working order again. The small changes are like: from TX <= RX to TX <= '0' or TX <= (not RX). They have nothing to do with the EDK project.
Adding debug information and tracing into the code with a debugger, we found that the software crashes as soon as the FLASH is read from. We don't understand what is causing it. We are concerned about the timing error, but the DDR2 read/write work OK and they are the only ones involving 5ns clock.
Has anybody had similar problem before? Any ideas? Any reply will be appreciated. MHS/MSS files are available upon request. ISE/EDK version 10.1. The device used is Virtex-4 FX60. The Flash chip is S29GL512P by Spansion.