Hi,I modify the ddr related design of xilinx ug1234 reference design,and meet some error during synthesis.How to solve these error?
Environment : 1. Vivado : 2017.22. OS : CentOS7.3
[Synth 8-439] error screenshot: 1. error message
2. Why bd_2fd7 show some unknown file?
I did modify the u_ocl_region IP,but the upgrade button can not be pressed.
3. The design hierarchy of interconnect_aximm_host IP.
4. The design hierarchy of u_ocl_region IP.
The method I tried :1. Reset output products
2. Generate output products