cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
630 Views
Registered: ‎11-21-2017

[Synth 8-439] module *** not found error, in vivado 2017.2 (modify from UG1234 reference design)

Hi,
I modify the ddr related design of xilinx ug1234 reference design,and meet some error during synthesis.
How to solve these error?

 

Environment :
1. Vivado : 2017.2
2. OS : CentOS7.3

 

[Synth 8-439] error screenshot:
1. error message

Screenshot from 2018-02-08 15-52-03.jpg

 

2. Why bd_2fd7 show some unknown file?

I did modify the u_ocl_region IP,but the upgrade button can not be pressed.

Screenshot from 2018-02-08 15-54-08.jpg

 

3. The design hierarchy of interconnect_aximm_host IP.

Screenshot from 2018-02-08 15-55-16.jpg

 

4. The design hierarchy of u_ocl_region IP.

Screenshot from 2018-02-08 15-55-48.jpg

 

The method I tried :
1. Reset output products

reset_output_products.jpg

 

2. Generate output products

generate_output_product.jpg

 

Thanks.

0 Kudos
0 Replies