I have a a peripheral VHDL with AXI4lite bus in communication with MicroBlaze. Into this peripheral there is a block done with System Generator for signal processing.
When I generate the bitstream (processor + peripheral), in the map report all blocks of system generator are removed and in the summary view I see only the DSP of Microblaze. Why the block of sysgen is removed?
In the creation of the peripheral in XPS, I imported 2 files vhd of sysgen ( toplevel.vhd and toplevel_cw.vhd) and all ngc files generated. What I forget?
The block of sysgen doesn't talk with processor, therefore I don't need EDK processor in system generator.