02-21-2019 12:21 PM
I have a project coming up in 2 weeks. So, I'm looking for AXI4 design in SystemVerilog to verify and emulate. It would be very helpful if anyone in this forum could provide me a design.
02-21-2019 01:25 PM
Ya, I was looking at AXI lite as well, but could not find a proper design. This document is very useful, thank you!
Do you have a design code of AXI lite?
02-21-2019 01:55 PM