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Observer
Observer
12,123 Views
Registered: ‎02-13-2008

TEMAC Evaluation Licensing Troubles

Hello,

 

I am a University of Florida student developing atop Stanford's NetFPGA (http://netfpga.org) platform with their reference NIC architecture, which uses a Virtex II Pro 50 FPGA.  This architecture uses a Tri-mode Ethernet Mac Core (TEMAC), version 3.

 

My issue is that I cannot generate a bitstream for the TEMAC IP core, due to a licensing error.

 

I am attempting to compile it using ISE 9.2i on a Ubuntu Linux 8.04 PC.  I obtained a "full system evaluation license", using my host ID (generated by running 'hostid' on the terminal).  I first attempted to supply my MAC address, but only 'hostid' generated an ID which fit on the form.  To install the license, I downloaded the .zip file Xilinx sent to me by e-mail in my home folder, and ran the following:

 

source ~/Xilinx92i/settings.sh

cd ~

sudo $XILINX/bin/lin/unzip core_licenses_eval.zip

 

Which run without problems.  Then I ran the makefile supplied by the NetFPGA architecture for generating the bit file.  It exits with the following error:

 

ERROR:Bitgen:169 - This design contains one or more evaluation cores for which
   bitstream generation is not supported. Please see the informational messages
   in the NGDBUILD report file for this design, <designname>.bld, to determine
   which core causes this error.

 

The bld file, nf2_top.bld, contains the following error:

 

INFO:coreutil - License for component <tri_mode_eth_mac_v3> found, but this
   license does not allow you to generate bitstreams for designs that
   incorporate this component. You may generate functional simulation netlists,
   but you may not evaluate this component in hardware.
   For ordering information, please refer to the
   product page for this component on www.xilinx.com

 

The TEMAC product page states that the Full system Evaluation License allows me to program the core on a Xilinx FPGA device.  Have I made any mistakes when installing this license, and what should I try and do to make it generate the bitstream? 

 

Thank you in advance.

 

EDIT:  After looking on coregen, it lists the IP status as such:

Status type: FLEXlm

Status:  FLEXlm error - no such feature exists (-5.21)

 

EDIT:  I managed to enter my full mac address after filling out the evaluation form as a Windows user and switching to "Linux" at the last minute.  After re-installing the license, the status now shows up as:

Status type: FLEXlm

Status:  Hardware Evaluation

 

However, I still get the error messages described in the post.

 

Message Edited by joeantoon on 06-16-2008 12:32 PM
Message Edited by joeantoon on 06-16-2008 12:41 PM
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6 Replies
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Xilinx Employee
Xilinx Employee
12,117 Views
Registered: ‎08-02-2007

Initially it looks like you didn't have the correct license. From the errors I can see that the tools were seeing a "Simulation Only" license rather than the generated license. In your last update the license status says "Hardware Eval". This means that the license file you generated was not the "FULL" license file. This type of license should allow you to generate a bitstream with no errors. You will get a warning in bitgen that states that the design will time out after some time period.

 

For the FULL license, go back to the license generator in the core lounge and select "Generate a Full License key for the soft Tri-Mode Ethernet MAC".Make sure you have the correct HOSTID andpick the correct "License Server Platform" value.

 

If you have any more issues I would suggest opening a webcase at www.xilinx.com/support.  

 

RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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Observer
Observer
12,113 Views
Registered: ‎02-13-2008

Thank you for your quick reply.  I attempted to access your link, but it requires a serial number for a TEMAC purchase.

 

I am not able, at this time, to purchase a full license for the core.  Until I can obtain one, I would like to continue my research with the Hardware Evaluation, found here:

 

http://www.xilinx.com/ipcenter/ipevaluation/member/temac_eval_request.htm

 

From this page, it claims that this evaluation license can be used for up to 8 hours of hardware testing at a time:

"You will also be able to perform functional and timing simulation as well as create a bitstream, and download and configure your design in hardware. The IP will be fully functional for approximately 8 hours, after which it will "time out" and you will need to download and configure the FPGA again."

 

This license is the one I have been attempting to use in the post.

 

EDIT:

 After running "make clean" and regenerating the architecture, the nf2_top.bld file now shows this:

Applying constraints in "nf2_top.ucf" to the design...
INFO:coreutil - License for component <tri_mode_eth_mac_v3> found, but the
   generated design will cease to function in the programmed device after
   operating for some period of time. This allows you to evaluate the component
   in hardware. You are encouraged to license this component.

   The license for this core was generated for joe.antoon@ufl.edu on June 16,
   2008. It is the responsibility of the Licensee of this core to adhere to the
   site restriction and other terms of the Xilinx Core Site License Agreement
   when using this core.

   For ordering information, please refer to the
   product page for this component on www.xilinx.com

 

Which is great.  However, I still get the licensing error, and no bitfile.

ERROR:Bitgen:169 - This design contains one or more evaluation cores for which
   bitstream generation is not supported. Please see the informational messages
   in the NGDBUILD report file for this design, <designname>.bld, to determine
   which core causes this error.

Message Edited by joeantoon on 06-16-2008 01:15 PM
Message Edited by joeantoon on 06-16-2008 01:22 PM
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Xilinx Employee
Xilinx Employee
12,110 Views
Registered: ‎08-02-2007

yes, for the Hardware Eval license it will time out after some amount of time. This is roughly 8 hrs and will vary based on the design clock. If you are getting the same errors as before you generated the HW eval license you might need to clear the coregen cache. When you open Coregen and look at the license status you should see a button for clearing the cache. After clearing the cache you should restart coregen. After generating the core you should be able to generate all the way to bitstream.
RJ Duran
Customer Application Engineer
Technical Support: http://www.xilinx.com/support
Xilinx User Community: http://forums.xilinx.com
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Observer
Observer
12,091 Views
Registered: ‎02-13-2008

Flushing the cache did not seem to work.

 

However, to get a list of IPs, I had to start a new project in Coregen.   Is the coregen cache separate for each project?  If so, this architecture is generated by running a makefile from the command line.  Is there a way to flush the cache from there?

 

EDIT:  OK, I cleared the license cache ("$XILINX/bin/lin/xlicmgr reset -v") from the terminal and that did not work.  It still reports bitgen 169 without specifying a licensing error in the .bld file.  I have also rebooted the computer and run "make clean" before rebuilding.

 

EDIT: Here are the output and .bld file generated by bitgen:

http://betterwebber.com/temac_error.zip

 

EDIT Also, here is the command that generates the error:

bitgen -intstyle ise -g Binary:No -w nf2_top_par.ncd

Message Edited by joeantoon on 06-16-2008 02:50 PM
Message Edited by joeantoon on 06-16-2008 03:33 PM
Message Edited by joeantoon on 06-17-2008 11:00 AM
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Visitor
Visitor
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Registered: ‎11-08-2008

I was having this same problem.  It appears that Coregen uses the MAC addr of "eth0" to identify the host machine.  The MAC address I was using (which was the MAC address of my network card) was for "eth1".  To resolve this I simply swapped the names of "eth0" and "eth1" in /etc/udev/rules.d/70-net_persistent_names.rules

 

-Jorge

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Observer
Observer
9,223 Views
Registered: ‎07-02-2008

I recently had a similar problem with "ERROR:Bitgen:169" and it turned out to be because the netlists for the generated IP (the NGC files) had been generated on a PC that didn't have the licensing setup.  Regenerating the cores in CoreGEN on my own PC, where the licenses were setup correctly, then rebuilding resolved the problem.

 

Since you did basically the same thing I did (generated the cores, then installed the licenses for them, then tried to build), I'm guessing this is the same issue you are seeing, and that regenerating the netlists in CoreGEN will resolve the issue.

Message Edited by kerryhj on 01-27-2009 12:26 PM
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