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talvlad29
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Registered: ‎05-28-2019

TLAST signal control

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Hello,

I am using Axi dma in my design to transfer data from ADC throughout FIFO (Stream Data FIFO IP) to DDR(S2MM only). I disabled packet mode for DMA because the FIFO is filled up by ADC samples continuously. TLAST output signal (m_axis_tlast) from FIFO to DMA was enabled but FIFO did not generated it until FIFO s_axis_tlad was managed (I temporary set s_axis_tlast FIFO every 1024 samples). I used a baremetal application (cortexr5_0) for testing my design and I received DMA error interrupt every transaction until added FIFO s_axis_tlast control in my design. My question is how/why I have to use TLAST signal in non-packet DMA mode. TLAST control does not make sense for me if I use ADC data stream. 

Thank you,

Vladimir

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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Hi @talvlad29 

  The AXI DMA supports the multi-channel feature and that's how the channels are separated: by a combination of TDEST and delimited with TLAST. This multi-channel feature may be obsoleted/removed at some point, because it was split into the new AXI MCDMA IP.

  In the one channel case, TLAST can be used to signal the end of a buffer and to force the utilization of a new block descriptor.

Thanks,

-Pat

 

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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Hi @talvlad29 

  The AXI DMA supports the multi-channel feature and that's how the channels are separated: by a combination of TDEST and delimited with TLAST. This multi-channel feature may be obsoleted/removed at some point, because it was split into the new AXI MCDMA IP.

  In the one channel case, TLAST can be used to signal the end of a buffer and to force the utilization of a new block descriptor.

Thanks,

-Pat

 

Give kudos if helpful. Accept as solution if it solves your problem.
https://tuxengineering.com/blog

View solution in original post

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talvlad29
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Registered: ‎05-28-2019

Thank you for clarification. 

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