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liuhaha
Visitor
Visitor
7,782 Views
Registered: ‎07-27-2015

The problem of AXI GPIO constraint in Vivado

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Hi, guys

I am using zc702.

I have added an IP of axi_gpio to my project and set its width to 1.

2016-05-14_223904.png

And I added the constraint that as follow:

set_property  -dict {PACKAGE_PIN  P17  IOSTANDARD LVCMOS25} [ get_ports gpio_rtl_tri_o[0] ] ;

to control  a led.

 

During Implementation, Vivado display three errors:

[Common 17-55] 'set_property' expects at least one object.

 

 

I have examined my code ,the port name is right because the top HDL code have been automatic added the following code:

assign gpio_rtl_tri_o[0] = axi_gpio_0_GPIO_TRI_O;

 

I dont know why it has error.

 

Then I set the GPIO width to 2, and modify the constraint as follow:

set_property  -dict {PACKAGE_PIN  P17  IOSTANDARD LVCMOS25} [get_ports gpio_rtl_tri_o[0]];
set_property  -dict {PACKAGE_PIN  P18  IOSTANDARD LVCMOS25} [get_ports gpio_rtl_tri_o[1]];

 

 

All error have disappeared.

 

That meas the width of GPIO can not be 1 ? Why? How should  I edit the constraint ?

 

Thanks,

Leo

 

 

 

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muzaffer
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Registered: ‎03-31-2012
try: set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [ get_ports gpio_rtl_tri_o] ;
- Please mark the Answer as "Accept as solution" if information provided is helpful.
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muzaffer
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10,386 Views
Registered: ‎03-31-2012
try: set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [ get_ports gpio_rtl_tri_o] ;
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

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