cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
nadales
Observer
Observer
575 Views
Registered: ‎06-11-2019

Transmission time FPGA CPU Zynq

Hello all,

This is my problem: 

I have Zynq processor. I have connected a module implemented on the PL part to the PS part. I'm sending data form the PS part to the PS part and vice versa. I have employed Vitis IDE platform to create my software application in C. 

My question is:

How can I monitor the time it takes to send a new data from the PS to the PL? 

 

Thanks you very much.

Tags (3)
0 Kudos
5 Replies
dpaul24
Scholar
Scholar
565 Views
Registered: ‎08-07-2014

@nadales,

How can I monitor the time it takes to send a new data from the PS to the PL?

You Q might have multiple solutions. This is the one I can quickly think about.

The PS to PL communication is using the AXI4 protocol. Sending a new data means writing from the PS to the PL. So I will start a counter which will count the rising edges of the system clock when the AWVALID is asserted and keep counting, until the BVALID is asserted from the PL. That is the time taken in terms of your system clock.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem
Asking for solutions to problems via PM will be ignored.

0 Kudos
nadales
Observer
Observer
560 Views
Registered: ‎06-11-2019

Ok. Thank you very much for your reply. That could be the solution. Because I'm new to this, could you please tell me how can I access those AWVALID and BVALID signals and how to set up the counter you propose?

I really appreciate you help.

0 Kudos
544 Views
Registered: ‎07-23-2019

 

What is exactly "the time it takes to send a new data"?

- is it between the first bit sent and that same first bit received?

- is it between the first bit sent and the last bit received?

you might find things are not as regular as may think if DMA is involved, etc.

You could use the RTL simulation and look at how many clocks. Or else, a smarter real-time (more work) approach, have a counter triggered by the start event and stopped by the end event and look at the clock count with ILA/ VIO.

0 Kudos
dgisselq
Scholar
Scholar
467 Views
Registered: ‎05-21-2015

@nadales ,

This is a challenging question.  In general, you want to know the time from a request from the PS to the response returned to the PS.  A performance monitor of some type would be required to answer this question.

The problem is ... AXI is a difficult and challenging protocol to measure via a performance monitor.  For example, AXI allows multiple bursts to be outstanding, and for burst responses to be returned out of order.  How then do you answer the question of what the lag was through the system when different responses might see different amounts of lag?

Xilinx provides an AXI performance monitor capability.  I haven't tried using it myself.  I've also built my own.  My own performance monitor is just a series of counters, but you then need to decouple those counters to figure out which ones are relevant to the information you wish to measure.  You should find, embedded in that information, measures of both latency and throughput.  Perhaps those measures might give you an idea of what you are looking for.

Dan

0 Kudos
nadales
Observer
Observer
460 Views
Registered: ‎06-11-2019

Hi,

thanks for your answer and for sharing your code. I'll try it. I haven't solved my problem yet. 

 

0 Kudos