UART 16550 v2.0 In FIFO mode receives interrupt on every byte
I am running AXI UART 16550 implemented for ZCU102 evaluation board (UltraScale+).
Only Rx interrupt is enabled (Tx is disabled). FIFO is configured for any thrigger level other than 1, I have tried 14, 8, 4. I have cretated an example to count number of interrupt received and figured out that an interrupt is triggered for every incoming byte
What am I doing wrong?
Here is my initialization and IRQ function:
/* Set word length, stop bits, and parity based off configuration */