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sawbg
Newbie
Newbie
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Registered: ‎02-13-2020

UART2 Using Only HDL (& is AXI required?)

This is for the ZCU102 eval board, which uses a Zynq Ultrascale+ MPSoC.

I'm very new to firmware development. I’m trying to use the Uartlite IP to send data to a console terminal on the PC. This is a good learning experience for me. It’s given me the opportunity to read up on AXI as well as how the PL communicates with PS peripherals.

I’ve seen several examples online of the Uartlite IP (specifically for UART 2, with the PL) being used in block-diagram form, and these block diagrams use AXI, but they also incorporate several PS blocks and often C-code written in Xilinx SDK, which seems to violate a an HDL-only design directive I've been given for this project.

I’ve also ready that the Uartlite IP doesn’t have to be used with AXI, that you can interact with it directly. In other words, you don’t necessarily need the supporting IP blocks, such as AXI Interconnect and Processor System Reset. The Uartlite IP example project uses the AXI Traffic Generator IP, which seems to only be useful for testing, and the Uartlite IP documentation (PG142) doesn’t seem to specify how to use this block without the Traffic Generator.

I’ve created block diagrams (attached) with and without AXI, and I was hoping you could take a quick peak when you get a chance and tell me if it looks like I’m on the right track. Or do I need to spend more time trying to understand AXI and IP blocks? Could someone please point me in the correct direction to better understand whether I need the AXI interface and how I would use it in this case specifically?

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drjohnsmith
Teacher
Teacher
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Registered: ‎07-09-2009

The software you refere tois probably the C dirvers neeed to run on the processor in the FPGA to access the AXI uart.

if you want real small, but you are gogin to have to work, not just copy and paste,

try page 21

https://www.xilinx.com/support/documentation/white_papers/wp271.pdf

 

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