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pl_24
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Registered: ‎07-24-2020

Understanding AXI CDMA interrupt generation

Hello everyone,

We are working on a custom Memory management IP and use AXI CDMA for making AXI burst transfers from the memory(DDR) to the IP. ( ZYNQ MPSOC 19EG)

In the document https://www.xilinx.com/support/documentation/ip_documentation/axi_cdma/v4_1/pg034-axi-cdma.pdf (Page number -42, Heading- Interrupts), states : "Simple DMA mode generates an IOC interrupt whenever a programmed transfer is completed"

Questions :

1> What exactly does it mean by programmed transfer is completed in context of AXI CDMA  ? 

2> Is there any restriction on timing as in if IP doesn't get any response within x clock cycle, interrupt will not be generated ? (For example if AXI CDMA makes a read requests to slave and the response on RDATA arrives after x clock cycles)

3> When exactly is the interrupt generated ? ( is it generated on the BVALID High ??)

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