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Adventurer
Adventurer
543 Views
Registered: ‎06-04-2019

Updatemem not updating the BRAM

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Hello All,

I created a simple Microblaze design with AXI BRAM as shown in the below figure,MB1.PNG

Address editor,

addresseditormbram.PNG

I have attached the mmi file, mem file and the debug file from the updatemem command,

exec updatemem --debug --force --meminfo D:/tha/MB_BRAM/MB_BRAM.runs/impl_1/module1_wrapper.mmi --data D:/tha/MB_BRAM/MB_BRAM.srcs/sources_1/bd/module1/data1.mem --bit D:/tha/MB_BRAM/MB_BRAM.runs/impl_1/module1_wrapper.bit --proc module1_i/microblaze_0 --out download2.bit > updatemem_debug.tx

I see some random numbers 1, 2 here and there in the bit lanes. Can someone please explain me what is happeneing. Any help is appreciated!

****** updatemem v2018.3.1 (64-bit)
  **** SW Build 2489853 on Tue Mar 26 04:20:25 MDT 2019
  **** IP Build 2486929 on Tue Mar 26 06:44:21 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source D:/Xilinx/Vivado/2018.3/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo D:/tha/MB_BRAM/MB_BRAM.runs/impl_1/module1_wrapper.mmi -data D:/tha/MB_BRAM/MB_BRAM.srcs/sources_1/bd/module1/data1.mem -proc module1_i/microblaze_0 -bit D:/tha/MB_BRAM/MB_BRAM.runs/impl_1/module1_wrapper.bit -out download2.bit -force -debug

Dump the BRAM Initialization Strings. 
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y45
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  INIT_01:0000000000000000000000000000000000000000000000000000000000000000
  INIT_02:0000000000000000000000000000000000000000000000000000000000000000
  INIT_03:0000000000000000000000000000000000000000000000000000000000000000
  INIT_04:0000000000000000000000000000000000000000000000000000000000000000
  INIT_05:0000000000000000000000000000000000000000000000000000000000000000
  INIT_06:0000000000000000000000000000000000000000000000000000000000000000
  INIT_07:0000000000000000000000000000000000000000000000000000000000000000
  INIT_08:0000000000000000000000000000000000000000000000000000000000000000
  INIT_09:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0A:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0B:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0C:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0D:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0E:0000000000000000000000000000000000000000000000000000000000000000
  INIT_0F:0000000000000000000000000000000000000000000000000000000000000000
  INIT_10:0000000000000000000000000000000000000000000000000000000000000000
  INIT_11:0000000000000000000000000000000000000000000000000000000000000000
  INIT_12:0000000000000000000000000000000000000000000000000000000000000000
  INIT_13:0000000000000000000000000000000000000000000000000000000000000000
  INIT_14:0000000000000000000000000000000000000000000000000000000000000000
  INIT_15:0000000000000000000000000000000000000000000000000000000000000000
  INIT_16:0000000000000000000000000000000000000000000000000000000000000000
  INIT_17:0000000000000000000000000000000000000000000000000000000000000000
  INIT_18:0000000000000000000000000000000000000000000000000000000000000000
  INIT_19:0000000000000000000000000000000000000000000000000000000000000000
  INIT_1A:0000000000000000000000000000000000000000000000000000000000000000
  INIT_1B:0000000000000000000000000000000000000000000000000000000000000000

Version, Vivado 2018.3.1. Board: zcu111

Thanks,
Bhavanithya Thiraviaraja
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1 Solution

Accepted Solutions
Adventurer
Adventurer
527 Views
Registered: ‎06-04-2019

I read the mmi file structure in ug898 and I understood how the data is assigned. In my design, it seems the data is assigned bit by bit,

        <BitLane MemType="RAMB36" Placement="X5Y44">
          <DataWidth MSB="0" LSB="0"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

Each bit has a placement in the bus block and in some way the design assigns the bits distributed not in the same placement. So when I looked the first line of every placement in the debug output of updatemem,

****** updatemem v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source C:/Xilinx/Vivado/2018.3/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/MB_BRAM1.runs/impl_1/module1_wrapper.mmi -data C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/data1.mem -proc module1_i/microblaze_0 -bit C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/MB_BRAM1.runs/impl_1/module1_wrapper.bit -out download.bit -force -debug

Dump the BRAM Initialization Strings. 
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y44
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y50
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y20
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y18
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
 ----
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y23
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y48
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y40
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y50
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y57
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y52
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y44
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
------
  ^^^ Bitlane with BRAM Location: RAMB36_X8Y28
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y54
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y36
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y39
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X3Y34
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X3Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y10
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
------
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y42
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y38
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y40
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
-------- 
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y88
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y78
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y12
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y48
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X6Y15
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
--------- 

I could see my data, 1101 1110 0100 0001 0010.... i.e. DE412... which is the same data in data1.mem file.

And is seen in SDK in the memory but in a reversed way

memory.PNG

 

So I will close this issue now.!

 

 

Thanks,
Bhavanithya Thiraviaraja

View solution in original post

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1 Reply
Adventurer
Adventurer
528 Views
Registered: ‎06-04-2019

I read the mmi file structure in ug898 and I understood how the data is assigned. In my design, it seems the data is assigned bit by bit,

        <BitLane MemType="RAMB36" Placement="X5Y44">
          <DataWidth MSB="0" LSB="0"/>
          <AddressRange Begin="0" End="32767"/>
          <Parity ON="false" NumBits="0"/>
        </BitLane>

Each bit has a placement in the bus block and in some way the design assigns the bits distributed not in the same placement. So when I looked the first line of every placement in the debug output of updatemem,

****** updatemem v2018.3 (64-bit)
  **** SW Build 2405991 on Thu Dec  6 23:38:27 MST 2018
  **** IP Build 2404404 on Fri Dec  7 01:43:56 MST 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source C:/Xilinx/Vivado/2018.3/scripts/updatemem/main.tcl -notrace
Command: update_mem -meminfo C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/MB_BRAM1.runs/impl_1/module1_wrapper.mmi -data C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/data1.mem -proc module1_i/microblaze_0 -bit C:/Users/tha/Documents/VivadoProjects/MB_BRAM1/MB_BRAM1.runs/impl_1/module1_wrapper.bit -out download.bit -force -debug

Dump the BRAM Initialization Strings. 
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y44
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y50
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y20
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y18
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
 ----
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y23
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y48
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X2Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y40
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y50
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y57
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y52
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y44
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
------
  ^^^ Bitlane with BRAM Location: RAMB36_X8Y28
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y54
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y36
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y39
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X3Y34
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X3Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y10
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
------
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y42
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X4Y38
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y40
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
-------- 
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y88
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y46
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y78
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X5Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
-----
  ^^^ Bitlane with BRAM Location: RAMB36_X7Y12
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X10Y48
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
  ^^^ Bitlane with BRAM Location: RAMB36_X9Y16
  INIT_00:0000000000000000000000000000000000000000000000000000000000000000
  ^^^ Bitlane with BRAM Location: RAMB36_X6Y15
  INIT_00:0000000000000000000000000000000000000000000000000000000000000001
--------- 

I could see my data, 1101 1110 0100 0001 0010.... i.e. DE412... which is the same data in data1.mem file.

And is seen in SDK in the memory but in a reversed way

memory.PNG

 

So I will close this issue now.!

 

 

Thanks,
Bhavanithya Thiraviaraja

View solution in original post

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Reply