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tnet
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Using Memory/Registers on Zynq Zc702 for Data Transfer

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Hello,

 

 

I have an array of 2000 data points recorded (On Excel document). I want to implement logic in Verilog where it takes these data points that I feed it and chooses the largest value. I was going to implement logic where it does comparisons, so it takes 10 values from the 2000 data points collected and compares them and stores it in a register. It keeps doing comparisons in set of 10 values until all 2000 data points are compared and spits out the largest value. 

 

I wanted to do this in the least clock cycles because I'm assuming the processing for comparing will be a lot.

 

I was just confused on when it does the comparisons in sets of 10 values, it needs to store that value somewhere so it can start another comparison, until all 2000 data points are checked. They need to be temporary stored somewhere, so I wasn't sure how I access these registers.


Since I'm new to Verilog and I am using Vivado (zynq zc702 board), I was reading on the documents that there are NAND registers, and there is also DMA for SD, and others I2C,CAN,SPI, etc. Was a little confused on this. Could someone point me in the correct direction?

 

Zynq Documents I was looking at:

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug898-vivado-embedded-design.pdf

 

Thanks.

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hbucher
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@tnet  

I tried to give you the skinny on this

https://youtu.be/09wOWpZpLnI

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hbucher
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@tnet

Do you need to do this in verilog? What are the boundaries (equipment, tools) that you have? 

 

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tnet
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@hbucher

 

It needs to be done on a FPGA board. I have a Zynq ZC702 and was using Vivado Software. So, I was assuming this had to be done in verilog, unless I could do it in C also?

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u4223374
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For only 2000 data points, it'll probably be faster to ignore the FPGA and do them on the CPU (the ZC702 has a dual-core ARM Cortex-A9 CPU). The FPGA can do the comparison quickly, but just getting the data to and from the FPGA fabric will take more time than finding the largest value on the CPU.

 

The code for finding the largest value is trivial, of course. Just look through the array, keep track of what the largest value already found is, and if you find one larger then update it.

 

 

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tnet
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Hello,

 

Yes, the logic for finding the largest value is trivial and of less importance.

 

"For only 2000 data points, it'll probably be faster to ignore the FPGA and do them on the CPU (the ZC702 has a dual-core ARM Cortex-A9 CPU). The FPGA can do the comparison quickly,"

 

That is true, it does have a dual-core ARM Cortex-A9 CPU. My question from this is, do you have any guidance or document that shows how to implement this verilog file that has this logic on the ARM Cortex-A9 CPU? 

 

I know how to upload files onto a SD card and boot them with the board itself. That is what you mean correct?

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tnet
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hbucher
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@tnet You program the PL (FPGA) side with verilog. The CPU you program with the SDK, in C/C++. 

That is why I asked the first question - do you need to write it in Verilog or can you use C/C++?

 

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tnet
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@hbucher

 

I need to program both correct, To communicate between the FPGA and CPU using AXI Bridge.

 

So the program itself will be done on the FPGA, so verilog.

 

 

hbucher
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@tnet Ok that narrows it down.

I would create a very simple design with just the ZYNQ processor (PS).

https://www.xilinx.com/video/fpga/building-hardware-software-zc702-evaluation-kit.html

In this video, you dont even need the BRAM or the LED etc, just the processor. But dont forget to run the connection automation to preset the PS. 

Then package your verilog code inside an AXI component

https://www.youtube.com/watch?v=8hzzVhPw6uw

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug1119-vivado-creating-packaging-ip-tutorial.pdf

The easiest way to input the data would be really one by one through an AXI lite interface. You can create an interface with up to 1024 or 4096 registers if I can remember. Or you can just create two registers - one for input and the other for the result of the running result. Perhaps you need some sort of reset as well.

Hack into the wrapper code that Vivado creates and instantiate your component in there. It is very easy to see where the registers are assigned. It is then up to you to decide what to do with it. You can even delete the entire set of registers (that Vivado creates for you) and assign directly into your component. But you get the idea.

From the PS side all you have to do is to grab from xparameters.h the base address of your component and start poking the values - perhaps read from the UART (stdin) or even hardcoded in the binary for testing.

I am sure someone will come up with something astonishingly simpler than this but that's what comes to mind at this point.

Hope this helps...

 

 

 

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tnet
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@hbucher

 

I am already working with a pre-built Zynq processor (PS) design. Block diagram, bitstream, and synthesis have already been created and ran. I even created a "Blinking LEDs" project on it where it blinks the LEDs. I also exported it to the SDK and was able to load the BOOT.bin files onto a SD card and have the project "blinking LEDs" run on the board. 


I did that just to understand the board and how things work. So, I'm assuming I can skip the first link you provided.

 

Regarding the second/third link on "package your verilog code inside an AXI component ", and using the AXI lite interface... Should I follow that youtube video and document, are there certain page #'s on that document that will help me or should I read through and do the whole thing?

 

"Hack into the wrapper code", assuming to open and edit the file?

 

 

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hbucher
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@tnet  

I tried to give you the skinny on this

https://youtu.be/09wOWpZpLnI

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.

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tnet
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@hbucher

 

Thank You for taking the time and doing this, I will look at it and try it out!