11-11-2019 12:42 AM
Using Xspi_Transfer I am getting delay for CS to go High after data transfer i am get around 1 clk cycle delay how can i reduce the delay i want the cs to go high immediately after data transfer
11-11-2019 04:28 AM
11-11-2019 04:30 AM
Then how can i reduce the Delay is there any register level code for SPI transfer
11-13-2019 07:37 AM
We don`t have any specific register to define the delay between the data transfer and CS to be deasserted.
It is always depends on when you are deasserting the CS after the data transfer.
11-17-2019 10:37 PM
The Chip select is controlled by hardware i am not doing anything below is the thing iam doing
11-19-2019 07:39 PM
11-19-2019 07:43 PM
I am using Xspi set slave select function before transferring the data and CS is controlled by master core logic
01-05-2020 06:51 AM
There is some standard after how much time we should start the data transfer, it should not be immediatly after asserting the CS.