06-12-2018 09:31 AM
I have created an AXI-Lite slave with the Vivado IP creator (using the "Create AXI4 Peripheral" option). As the generated code should simply be VHDL code, I thought about testing the IP core using a testbench.
Now I would like to read from one register where I modified the output ( instead of reg0 a constant is written to reg_data_out).
As far as I understand AXI, the following signals are needed:
axi_arvalid <= '1';
axi_araddr <= "0000"; -- as I would like to read reg0.
Sadly there is no output on axi_rdata.
The reset is set to 1 and the clock is also working.
What am I missing?
06-13-2018 12:23 AM - edited 06-13-2018 12:30 AM
Additionally to the previously mentioned signals I set axi_rready to 1 because I am pretty sure this is necessary.