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Visitor
Visitor
766 Views
Registered: ‎04-22-2013

VDMA generates VDMADecErr

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System :

Vivado 18.2 on Windows 10 x64

 

Board:

Custom board with a ZYNQ XC7Z020 chip and 1GB DDR3 RAM.

 

The valid address range for RAM should be 0x00100000-0x3FFFFFFF.

In detail I have the following address map:

 

0x00100000-0x00FFFFFF        text.,.data,.bss,.heap etc. for CORE#0

0x01000000-0x1FFFFFFF        Memory for video-data (destination for VDMA1,2 S2MM over AXI-HP0

0x20100000-0x20FFFFFF        text.,.data,.bss,.heap etc. for CORE#1

0x21000000-0x3FFFFFFF        Memory for video-data (destination for VDMA3,4 S2MM over AXI-HP1

 

It’s a standalone application on both cores. I do not reprogram the MMU. Virtual and physical addresses are the same. Both cores can access the complete 1GB of DDR3 RAM.

 

There are two VDMAs (S2MM) connected via a smartconnect to each HP-Port. However, there is always only one of those two VDMAs running. VDMAs1,2 are connected to HP0 and VDMAs3,4 to HP1. Currently I am using only VDMA1 on HP0 and VDMA3 on HP1.

 

My problem is, that any VDMA generates a VDMADecErr, when accessing the address range above 0x20000000. When this occurs for the first time, I detected an error in the address editor, because the address range of all VDMAs started at 0x00000000 and the range was only 512M.

 

But changing the range to 1GB did not solve the problem. Then I did set the offset address for VDMA3,4 to 0x20000000 and the range back to 512M. I still get the VDMADecErr, when starting the VDMA at an address above 0x20000000.

 

The curious thing is, the VDMA is still working on addresses below 0x20000000, though it should not with these settings.

 

Any idea what can be wrong?

Where can I check the valid address range except in the address editor?

Do I have to change the address range anywhere else than in the address editor?

 

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Xilinx Employee
Xilinx Employee
829 Views
Registered: ‎10-04-2016

Hi @woitha,

If you delete and replace the AXI Interconnect (or SmartConnect) between the VDMA and the HP port in your Block Diagram, so you still see the issue? It sounds like the tools aren't properly detecting and updating the address decode ranges in the AXI Interconnect. 

 

Regards,

 

Deanna

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2 Replies
Xilinx Employee
Xilinx Employee
830 Views
Registered: ‎10-04-2016

Hi @woitha,

If you delete and replace the AXI Interconnect (or SmartConnect) between the VDMA and the HP port in your Block Diagram, so you still see the issue? It sounds like the tools aren't properly detecting and updating the address decode ranges in the AXI Interconnect. 

 

Regards,

 

Deanna

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Visitor
Visitor
736 Views
Registered: ‎04-22-2013

Yes, this did solve the problem. I did set all VDMAs to offset 0x0000_0000 and range 1G. Then I did delete the SmartConnects and replaced them. Now I can access addresses above 0x2000_0000. Thank you very much!