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Adventurer
Adventurer
5,342 Views
Registered: ‎02-13-2016

VGA Implementation Hardware Image Generator

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Hello,

 

I am working on implementing a VGA interface on my ZYBO Zynq board. The application is simple, I control the image on the screen using assigned RGB switches on the board.

 

The application is included in a tutorial, where it's mentioned that the circuit operates at 25 MHz.

 

Synthesis works fine. I get the following problems attempting the implementation stage:

 

error.JPG

 

Attached, the VHDL code, and the .xdc constraints file.

 

Questions:

1) How to overcome these problems?

2) When to use Package_Pin and IOStandard LVCMOS, whether separately or together?

3) How to assign clock constraint for  a given project with specific frequency? (I tried to do this with many simple applications, and all failed to implement the clock frequency I assign)

 

Thanks!

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Xilinx Employee
Xilinx Employee
10,084 Views
Registered: ‎08-01-2008

The BIVC-1 error message indicates that there are conflicting IOSTANDARDs in one bank.

These IOSTANDARDs require different VCCOs.

The following debug steps can be used to analyze the indicated conflict:

  1. Open the synthesized design.
  2. Check the ports in the I/O Ports window to examine the IOSTANDARD, Bank assignments, and other relevant attributes.
  3. Check the device SelectIO Resources User Guide (for example, (UG471) for 7 series devices) for details of IOSTANDARD conflicts.
 
For this design, sys_rst is LVCMOS33, requiring VCCO=3.3v and sys_clk_p is an LVDS_25 input.

As per (UG471), if the LVDS_25 input needs to use VCCO other than 2.5v, its DIFF_TERM property should be false.

By running the command below in the Tcl Console, it is found that the DIFF_TERM of sys_clk_p is 1:

get_property DIFF_TERM [get_ports sys_clk_p]


This issue can be resolved by setting DIFF_TERM property of sys_clk_p to false, as in the following example:

set_property DIFF_TERM false [get_ports sys_clk_p]

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
10,085 Views
Registered: ‎08-01-2008

The BIVC-1 error message indicates that there are conflicting IOSTANDARDs in one bank.

These IOSTANDARDs require different VCCOs.

The following debug steps can be used to analyze the indicated conflict:

  1. Open the synthesized design.
  2. Check the ports in the I/O Ports window to examine the IOSTANDARD, Bank assignments, and other relevant attributes.
  3. Check the device SelectIO Resources User Guide (for example, (UG471) for 7 series devices) for details of IOSTANDARD conflicts.
 
For this design, sys_rst is LVCMOS33, requiring VCCO=3.3v and sys_clk_p is an LVDS_25 input.

As per (UG471), if the LVDS_25 input needs to use VCCO other than 2.5v, its DIFF_TERM property should be false.

By running the command below in the Tcl Console, it is found that the DIFF_TERM of sys_clk_p is 1:

get_property DIFF_TERM [get_ports sys_clk_p]


This issue can be resolved by setting DIFF_TERM property of sys_clk_p to false, as in the following example:

set_property DIFF_TERM false [get_ports sys_clk_p]

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

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Xilinx Employee
Xilinx Employee
5,315 Views
Registered: ‎08-01-2008
related post
https://forums.xilinx.com/t5/Memory-Interfaces/DRC-error-Conflicting-Vcc-voltages/td-p/696833
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Adventurer
Adventurer
5,309 Views
Registered: ‎02-13-2016

@balkris Actually I got to that page before posting here, and I could not really get how to do these steps.

 

Also, I hope there's a possibility that you would, kindly, help me with my other questions.

 

Thanks

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Xilinx Employee
Xilinx Employee
5,306 Views
Registered: ‎08-01-2008

2) When to use Package_Pin and IOStandard LVCMOS, whether separately or together?
[] you can use together

Thanks and Regards
Balkrishan
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Adventurer
Adventurer
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Registered: ‎02-13-2016

When I checked the IO Ports, I found out that the default of the Vivado is to set all the ports to the LVCMOS18, while I use LVCMOS3 in my ZYBO.

 

Thanks a lot.

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