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Explorer
Explorer
6,217 Views
Registered: ‎01-18-2014

VHDL code and PS in ZedBoard

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Hi...

 

I have 2 sections in my design: VHDL coding for a part and interfacing with an external device via PS MIO pins.

I want to take the data received in PS to the input of the VHDL code written.

 

i have read about creating a custom axi ip from the HDL code and then use it with the PS.

 

 

Or is there a method like i can instantiate this code to the VHDL code generated from the block design??

If then, how would we add these ports to the HDL code generated for the block design??

 

Which method could be used??

Or is there any other way to do this??

 

Thanks in advance

 

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Explorer
Explorer
10,107 Views
Registered: ‎01-18-2014

I interfaced the VHDL code and the PS using the second method.

 

After completing the block design, i created a port and changed its type to 'clock' and 'output', named it as 'fabric_clk'. I connected this port to the F_CLK0 from the PS. So, when i generated the wrapper file, this pin also appeared in the ports list.

 

Next i added my vhdl code to the project and set this one as my top module. I instantiated the block design in my top module and added all the ports of block design as ports of the vhdl code also.

 

The thing to be noted is that, there is no need of a clk port in the vhdl code because the clock for the vhdl code should be the fabric clk (since the vhdl code will reside in the fpga part).

 

Next thing would be the addition of the constraints file to the project. In the constraints file, you only need to metion those ports in vhdl logic other than that of the block design.

 

The design is completed and it worked...

 

I hope this too is a correct method and thought of sharing this so that it may be helpful for some one later.

 

thanks 

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Observer
Observer
6,202 Views
Registered: ‎12-13-2013

It sounds like what you want to do is to create a custom IP using your code. The wizard in Vivado will help you define the interface you want your IP to have with the PS (register based, streaming, etc...) and if your IP is a master or a slave. Your IP can have multiple interfaces as well, or act like a master and a slave. Vivado will then generate the higher level HDL for you, defining the ports to communicate with the processor and how they are used. You will need to add your HDL to the custom IP as sources, and instantiate the top level as a components in the Vivado generated HDL's lowest level. If you have signals in your IP that need to be routed to other blocks in your design, you can add them as ports on every level upwards. The IP packager will then help you package your IP so that you may add your IP as a block and connect its ports to other modules. From there you can use the PS to talk to your IP and vice versa. 

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Explorer
Explorer
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Registered: ‎01-18-2014

Thank you shawayek for your reply...

 

When is the second method mentioned in my post applicable??

 

I have seen a blog which uses this..

 

http://svenand.blogdrive.com/archive/176.html#.VKynl9KUcqM

 

So, when can this method be used??

 

 

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Moderator
Moderator
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Registered: ‎04-17-2011
Creating a custom peripheral is a good approach. If you are new to it, try the tutorial: http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug1119-vivado-creating-packaging-ip-tutorial.pdf
Regards,
Debraj
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Explorer
Explorer
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Registered: ‎01-18-2014

I interfaced the VHDL code and the PS using the second method.

 

After completing the block design, i created a port and changed its type to 'clock' and 'output', named it as 'fabric_clk'. I connected this port to the F_CLK0 from the PS. So, when i generated the wrapper file, this pin also appeared in the ports list.

 

Next i added my vhdl code to the project and set this one as my top module. I instantiated the block design in my top module and added all the ports of block design as ports of the vhdl code also.

 

The thing to be noted is that, there is no need of a clk port in the vhdl code because the clock for the vhdl code should be the fabric clk (since the vhdl code will reside in the fpga part).

 

Next thing would be the addition of the constraints file to the project. In the constraints file, you only need to metion those ports in vhdl logic other than that of the block design.

 

The design is completed and it worked...

 

I hope this too is a correct method and thought of sharing this so that it may be helpful for some one later.

 

thanks 

View solution in original post

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