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guoxuknight
Visitor
Visitor
11,192 Views
Registered: ‎11-09-2007

Virtex5 ml501 Error: Processor under reset

I am getting the error described below when I create a baseline using BSB. 
 
Using XPS 9.2
Using a jtag cable to download the bitstream directly to the fpga
Using bootloop initialized to the BRAMs
 
 
Below is the information related to the error:
 
JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       f5059093          16        XCF32P
 2       59608093           8        xc95144xl
 3       0a001093           8        System_ACE
 4       22896093          10        XC5VLX50_U
MicroBlaze Processor Configuration :
-------------------------------------
Version............................7.00.b
Optimization.......................Performance
Interconnect.......................PLBv46
MMU Type...........................No_MMU
No of PC Breakpoints...............1
No of Read Addr/Data Watchpoints...0
No of Write Addr/Data Watchpoints..0
Instruction Cache Support..........off
Data Cache Support.................off
Exceptions  Support................off
FPU  Support.......................off
Hard Divider Support...............off
Hard Multiplier Support............on - (Mul32)
Barrel Shifter Support.............off
MSR clr/set Instruction Support....on
Compare Instruction Support........on

 ERROR: MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and it
s Bus Interfaces are connected properly
        UNABLE to STOP MicroBlaze
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5 Replies
centaur19
Xilinx Employee
Xilinx Employee
11,136 Views
Registered: ‎08-01-2007

The first thing I would check is if you have initialized the bitstream with atleast the bootloop.

HTH....


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guoxuknight
Visitor
Visitor
11,098 Views
Registered: ‎11-09-2007

First, Thanks for responding.

Often I have forgotten to initialize the bootloop but in this case the bootloop has been initialized as described in the post by:

"Using bootloop initialized to the BRAMs"

What is more interesting is that when using XPS 9.2 to create a base system design it works for the Spartan 3E starter kit we have but doesn't work for the virtex5.  Therefore we started comparing the mhs files next.  At that point we noticed only a small difference in the processor reset module.  Which makes sense and may explain why bsb choose the option to be this way.

The difference is that the external reset is set to 1 in the Spartan 3E base system design but its set to 0 on the virtex5 design.  Therefore we tried switch the 0 to a 1 and we get an error saying the external reset pin is connected an active low reset pin or something along those lines. 

So we then begin looking at the memory controller MPMC v3.0b and realize that the memory module is not configured for our particular ram.  We attempt find our part number but can not find it in the list.  The part number of our memory (256 Micron based ram) part number is MT4HTF3264HY - 53EB4.

We are unsure if this is related to the problem but, we think it may be since the problem is related to resetting and the only difference we noticed is the difference in the two processor reset modules.

Also a cleaned version of the base system design is attached to this message.

Thanks

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centaur19
Xilinx Employee
Xilinx Employee
11,094 Views
Registered: ‎08-01-2007

You are right that the external memory doesnt really have much to do with this.

If you are concerned about the reset polarities, I would suggest starting with a smaller system (Microblaze, LMB BRAM) and you can simulate it as well to rule out this possibility. If you can connect to Microblaze in this system, then you can go ahead and add the rest of the peripherals required.

Since it is ML501 board, the BSB should set the reset automatically for you. Does that design not work for you?


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guoxuknight
Visitor
Visitor
11,091 Views
Registered: ‎11-09-2007

Just to answer your question:

Since it is ML501 board, the BSB should set the reset automatically for you. Does that design not work for you?

The design straight from the BSB does not work.  The design I attached is exactly the design the BSB creates and it does not work for me.  As you can imagine, this is suprising. 

I use the same setup with the same xps to create a design for spartan 3e and it works so I'm not sure what is wrong.  Were using USB platform jtag module to directly download the bitstream to the fpga.  I also don't think we have to configure anything on the board physically since older system designs seem to work on the virtex5.  However, we would like to use the newer technologies.

We will try your suggestions such as using a very simple base design and trying simulation.

Thanks
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centaur19
Xilinx Employee
Xilinx Employee
11,087 Views
Registered: ‎08-01-2007

This is odd! Have you tried to run the memory test on the board? Do you see the output on the hyperterminal?

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