03-23-2020 06:27 AM
I am working on a project migration from Spartan6 to Zynq UltraScale+.
The HDL code used for Spartan6 uses an ODDR (Output Double Data Rate Output Register with Set, Reset and Clock Enable) component (https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
Vivado 2019.2's ODDR IP seems a totally different core, with just clock_in and clock_out:
What could I use in Zynq UltraScale+ architecture from Vivado 2019.2 IP repos as ODDR substitution ?
03-23-2020 06:36 AM
That looks like a bug in the IP catalog. Look in Tools=>Language Templates =><family>=>I/O Components=>Output DDR Register and you will see the correct instantiation. For VHDL, it looks like this:
ODDR_inst : ODDR generic map( DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" INIT => '0', -- Initial value for Q port ('1' or '0') SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC") port map ( Q => Q, -- 1-bit DDR output C => C, -- 1-bit clock input CE => CE, -- 1-bit clock enable input D1 => D1, -- 1-bit data input (positive edge) D2 => D2, -- 1-bit data input (negative edge) R => R, -- 1-bit reset input S => S -- 1-bit set input );