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Scholar
Scholar
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Registered: ‎05-14-2017

[Vivado 2019.2] Artix-7 ODDR component substitution for Zynq ?

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Hi,

I am working on a project migration from Spartan6 to Zynq UltraScale+.

The HDL code used for Spartan6 uses an ODDR (Output Double Data Rate Output Register with Set, Reset and Clock Enable) component (https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

ug471_oddr.gif

Vivado 2019.2's ODDR IP seems a totally different core, with just clock_in and clock_out:

Screenshot_2020-03-23_14-22-21.png

What could I use in Zynq UltraScale+ architecture from Vivado 2019.2 IP repos as ODDR substitution ?

Thanks,

s.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

Please reference the UltraScale Architecture Libraries Guide (UG974; v2019.2; pp 489-491).

forums_oddr.jpg

forums_oddr_2.jpg

forums_oddr_3.jpg

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Registered: ‎06-21-2017

That looks like a bug in the IP catalog.  Look in Tools=>Language Templates =><family>=>I/O Components=>Output DDR Register and you will see the correct instantiation.  For VHDL, it looks like this:

   ODDR_inst : ODDR
   generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" 
      INIT => '0',   -- Initial value for Q port ('1' or '0')
      SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
   port map (
      Q => Q,   -- 1-bit DDR output
      C => C,    -- 1-bit clock input
      CE => CE,  -- 1-bit clock enable input
      D1 => D1,  -- 1-bit data input (positive edge)
      D2 => D2,  -- 1-bit data input (negative edge)
      R => R,    -- 1-bit reset input
      S => S     -- 1-bit set input
   );
  

 

 

Highlighted
Xilinx Employee
Xilinx Employee
481 Views
Registered: ‎11-30-2007

Please reference the UltraScale Architecture Libraries Guide (UG974; v2019.2; pp 489-491).

forums_oddr.jpg

forums_oddr_2.jpg

forums_oddr_3.jpg

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Scholar
Scholar
409 Views
Registered: ‎05-14-2017

Thanks.

s.

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Scholar
Scholar
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Registered: ‎05-14-2017
@bruce_karaffa, not really a bug.
The problem (if we can call it as such) is that the libraries and IP cores changes from arch to arch.
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