07-24-2020 05:43 AM
I designed an AXI slave in which the data bus width is a parameter called i.e. AXI_DATA_WIDTH
I instantiated the IP with AXI_DATA_WIDTH=128, generated the bitstream and after testing the design in a ZCU102 board, was able to see that things were not working expected.
Then, I decided to use ILA to find the root cause of the problem.
I opened the synthesized design, clicked "set up debug" and started adding the signals I wanted to probe.
What I was able to notice was the the AXI_WDATA signal of the IP was only 32-bits (and not 128) as I intended.
This explains why my IP is not working as I intended.
I am using Vivado 2018.3 (which is still officially supported) and I believe this is a bug.
I d appreciate a solution from Xilinx.
07-27-2020 04:28 AM
07-24-2020 12:58 PM - edited 07-24-2020 01:06 PM
Could you please tell me what is the width of the MASTER AXI, which is connected to your SLAVE AXI? If the VIVADO generates bitstream without any errors, it means that M AXI and S AXI have the same width, otherwise it would report an error of width mismatch!
What I can guess, probably, your IP doesn't see (or better to be said the change you make is not propagated across all the generated codes, which is a Vivado bug persists also in Vivado 2016.3) your modification.
Please retry also the following workaround. When you are in the packaging environment, on the packaging steps pane, please click on the "Customization GUI". Then, on the right side, there would be opened new hierarchical windows with the parameter lets say " C S00 AXI TDATA WIDTH ". Now, double click on this parameter and change the editable option to "yes". Finally, to have the different options of different data widths, on the bottom of the current window you can add how many data widths options that you desired. In the end, click OK and re-package your IP. Now, in your main design when you instantiate your IP, by double-clicking on it you can edit the AXI data width to your preset options.
hope this helps!
07-27-2020 02:29 AM
in the block design diagram, both the data interfaces of the slave (myip) and the master (axi smc) are 128 bits. (See first figure below).
After I run the synthesis and start selecting signals to debug, however, myip has only a 32-bit data interface (see second figure below) and the axi_smc has a 128-bit interface (see third figure below).
I tried the approach you proposed and still run into the same problem.
Anything else I could try?
07-27-2020 03:37 AM
I have some new info: I have hardcoded the values passed through parameters into the module, this means that AXI_WDATA and AXI_RDATA are declared as having a width of 128 instead of having a width of AXI_WIDTH (a parameter).
Still, after synthesis, it seems like vivado reverts the data bus width to 32.... this is strange.
07-27-2020 04:28 AM