Platform: ZCU102 (bare-metal), booting from SD-card
I'm an research assistant at a university, and we're getting ready to do some radiation tests on the Ultrascale+ hardware later this year. For the tests we want the watchdog timers to run in reset mode (without using any PL resources). I've had some success in getting them to work, but there are still some unresolved problems.
(I would have used an existing example, but I couldn't find any that addressed the particularities of the MPSoC.)
What I've done so far:
- Took the "polled" mode example from here, to use as a template.
- Changed it to enable the reset output of the watchdog timer.
- Wrote to the appropriate PMU registers to allow it to acknowledge the timer signal.
- Put the code into an infinite "while(1);" loop after starting the timer.
- Used a persistent global storage register to keep track of how many consecutive resets have happened. It prints out and increments the reset count at the beginning of main().
My code is attached if you need more detail (be aware it's a bit messy at the moment).
At this point what I have kind of works, but I'm having some issues:
- After the first reset, transmissions from the UART stop as soon as I give the PMU permission to acknowledge the watchdog reset signal, regardless of the amount of time the watchdog timer is set for. (UART transmissions resume once the reset occurs.) Thus, in order for the reset count to even print out after a reset, I need to insert a delay after the print statement; otherwise, the terminal receives nothing (or a corrupted character at best).
- After a random amount of resets (usually between 1 to 4), I stop receiving transmissions of any kind from the UART. (The code could still be running?)
- The PS_ERR_OUT LED on the dev board just stays on after the first reset. I assume there's just some flag I'm forgetting to reset.
- On page 223 of the MPSoC TRM it says "The APU SWDT can be used to reset the APU or the FPD. The RPU SWDT can be used to reset the RPU or the PS." How exactly can I specify the target? I haven't found anything in the register reference or TRM that sheds any more light on the subject.
Help or leads on any one of these questions would be tremendously helpful.
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For reference, here's a typical output when I insert a delay before activating the watchdog timer.
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 0
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 1
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 2
...and then it just stops.
And here's an typical output of the same code, except without the delay:
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 0
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
▒--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
...and again, it stops abruptly.
Thanks in advance.
