cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
a_west
Newbie
Newbie
10,153 Views
Registered: ‎07-29-2016

Watchdog Timer reset on Zynq Ultrascale+

Platform: ZCU102 (bare-metal), booting from SD-card

 

I'm an research assistant at a university, and we're getting ready to do some radiation tests on the Ultrascale+ hardware later this year. For the tests we want the watchdog timers to run in reset mode (without using any PL resources). I've had some success in getting them to work, but there are still some unresolved problems.

 

(I would have used an existing example, but I couldn't find any that addressed the particularities of the MPSoC.)

 

What I've done so far:

  • Took the "polled" mode example from here, to use as a template.
  • Changed it to enable the reset output of the watchdog timer.
  • Wrote to the appropriate PMU registers to allow it to acknowledge the timer signal.
  • Put the code into an infinite "while(1);" loop after starting the timer.
  • Used a persistent global storage register to keep track of how many consecutive resets have happened. It prints out and increments the reset count at the beginning of main().

My code is attached if you need more detail (be aware it's a bit messy at the moment).

 

At this point what I have kind of works, but I'm having some issues:

 

  1. After the first reset, transmissions from the UART stop as soon as I give the PMU permission to acknowledge the watchdog reset signal, regardless of the amount of time the watchdog timer is set for. (UART transmissions resume once the reset occurs.) Thus, in order for the reset count to even print out after a reset, I need to insert a delay after the print statement; otherwise, the terminal receives nothing (or a corrupted character at best).
  2. After a random amount of resets (usually between 1 to 4), I stop receiving transmissions of any kind from the UART. (The code could still be running?)
  3. The PS_ERR_OUT LED on the dev board just stays on after the first reset. I assume there's just some flag I'm forgetting to reset.
  4. On page 223 of the MPSoC TRM it says "The APU SWDT can be used to reset the APU or the FPD. The RPU SWDT can be used to reset the RPU or the PS." How exactly can I specify the target? I haven't found anything in the register reference or TRM that sheds any more light on the subject.

Help or leads on any one of these questions would be tremendously helpful.

 

---

 

For reference, here's a typical output when I insert a delay before activating the watchdog timer.

--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 0
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 1
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 2

 ...and then it just stops.

 

And here's an typical output of the same code, except without the delay:

--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
Resets: 0
--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL
▒--------------------------------------
Xilinx Zynq MP First Stage Boot Loader
Release 2016.1 Jul 28 2016 - 12:24:04
Platform: Silicon, Running on A53-0 (64-bit) Processor
SD1 Boot Mode
Exit from FSBL

...and again, it stops abruptly.

 

Thanks in advance.

0 Kudos
9 Replies
austin
Scholar
Scholar
10,147 Views
Registered: ‎02-27-2008

a_w,

 

Contact me:  austin@xilinx.com

 

Radiation testing is a incredibly tough task on Zynq 7 series (we did it), and ten times as tough on Zynq MPSoC.

 

We are planning our testing right now.  While we appreciate others coming to us or publishing the same data we have available, the benefit to the design communities by duplicating existing work is marginal.  What is more useful is to do something we are not already doing.

 

We can work on that together,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
ioanalin
Visitor
Visitor
7,549 Views
Registered: ‎02-10-2017

Hi,
We are working with the APU wdog timer and observed the following behaviour:
- If the wdog is set to trigger an IRQ, the IRQ comes.
- if the wdog is set to trigger a reset, then reset doesn't happen.

Are the following scenarious possible causes:
- the reset doesn't happen because of runnning in non-secure mode
- the reset doesn't happen because of NOT selecting what to reset: APU or the FPD.

Any help would be appreciated. Did we miss to set smth ?

Thanks,
Alin
0 Kudos
pvenugo
Moderator
Moderator
7,212 Views
Registered: ‎07-31-2012

Hi,

 

The reset might not happen if the RST_FPD_TOP[swdt_reset] ​ is not enabled which is for FPD i.e. accessible to APU.
Let me know if the this link which show WDT for Zynq MPSoC with example helps you http://www.wiki.xilinx.com/Cadence+WDT+Driver 

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
rogerrb1
Visitor
Visitor
5,781 Views
Registered: ‎06-23-2010

Hi,

 

According to AR# 69423 (https://www.xilinx.com/support/answers/69423.html), "On reset-on-timeout, the interrupt handler will call PMUFW APIs to reset both the PS and PL".  

 

Does this mean that proper operation of the hardware watchdog is dependent on software (the pmu firmware)?

 

0 Kudos
pvenugo
Moderator
Moderator
5,531 Views
Registered: ‎07-31-2012

Yes, for appropriate reset on timeout as in DT need to do it through PMUFW.

The attached patch usage will make WDT work.

 

Regards

Praveen


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
imshedi
Newbie
Newbie
5,125 Views
Registered: ‎01-29-2018

I got something on Mz-7z010, using persistent storage register. The user guide says (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) we can use upper 16 bits of multiboot register for persistent storage, for example keeping count of WDT resets. Find the attached C file. Hope it helps & please share your feedback.

0 Kudos
pvenugo
Moderator
Moderator
5,097 Views
Registered: ‎07-31-2012

Hi @imshedi,

 

The original query and the information posted are only relevant to Zynq Ultrascale devices.

Your findings are for Zynq 7000. 

Let me know what issue are you seeing exactly.

 

I'd appreciate if you can create a new post for Zynq-7000 WDT reset.

 

Regards

Praveen

-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------


-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
r1200gsa
Observer
Observer
4,862 Views
Registered: ‎03-15-2018

Hello,

 

I'm trying to use the SWDT from the APU (currently in "bare metal").

I have used the poll_example.

it seems that the WD counter works fine and sends a RESET request when it's no longer restarted, but I can't get a hardware  RESET.

I have tried to set the different PMU registers :

PMU_GLOBAL_ERROR_SRST_EN_1 , PMU_GLOBAL_ERROR_EN_1 (FPD_SWDT bit )

 and also I've tried to set the RST_FPD_TOP  swdt_reset bit but until now without any success.

 

Does anyone have a full programming example to reset the controller (as SRST pin do) from the SWDT ?

 

I'm using the debugger with a JTAG connection (on a ZCU102) to run the test, could it be a reason why the RESET is not generated ?

 

 Any help will be appreciated.

 

Philippe

 

 

0 Kudos
sonminh
Adventurer
Adventurer
1,110 Views
Registered: ‎10-02-2018

Hi @r1200gsa , @a_west , @imshedi , @rogerrb1 

Do you have run xwdtps_polled_example.c to reset zynqmp. I have XWdtPs_EnableOutput(&Watchdog, XWDTPS_RESET_SIGNAL); but once timeout watchdog, system and hardware not reset. I have package pmu firmware, fsbl, bitstream, and application into BOOT.bin

Thanks and brgs

0 Kudos