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Registered: ‎07-31-2012

Welcome to Processor System Design board

This board is intended to discuss Processor System design for Versal, Zynq UltraScale+, Zynq-7000, and MicroBlaze.

Few PS and PL peripherals covered in this board are Interrupts, Timers, GPIO, UART, PS-SPI, USB, SATA, I2C, UART, CAN, CAN-FD, RTC, and EPC.

This includes the Versal Control, Interface & Processing System (CIPS) Wizard and Processor Configuration Wizard (PCW) as well.

Also, AXI infrastructure IPs such as AXI-stream, interconnect, memory-mapped, DMA etc are included to this board.

Before posting query, please follow the below steps:

  1. Search in the forum previous discussed similar topics
  2. Refer to useful resources -> IP product guide , user guide, relevant Wiki page menitoned in Xilinx IP hardware and software collateral
  3. Search for relevant AR/Known issues, limitations online
  4. Post your questions


Before posting, please read Xilinx Community Forums Guidelines or to get started see our Community Forum Help.


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