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Adventurer
Adventurer
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Registered: ‎06-27-2016

What is the minimum clock latency for FSL instruction to write to axi_s link?

HI all,

Im trying to interface my ip with Microblaze FSL link.

MB FSL feature provide a axi_stream master/slave. While running putfslx(x0xx,0,FSL_DEFAULT) back to back(run as GDB via SDK)  getting a four cycle delay between the data.

Slave ready is set to high ensuring no back pressure.

Is there a way around to reduce it?

Attached a ila screenshot.

Screenshot from 2020-05-27 15-19-21.png
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