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ysjung
Participant
Participant
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Registered: ‎01-12-2020

What part of my block diagram needs to be constrained in the xdc file to see 32bit of data on the oscilloscope?

Hi

I am designing to put data into bram and send it to ddr through cdma.

First of all, I checked memory on sdk that the data is delivered to the bram well.

What I want to do is extract the data delivered by ddr and check it with the oscilloscope.

What part of my block diagram needs to be constrained in the xdc file to see 32bit of data on the oscilloscope?CDMA.PNG

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katsuki
Xilinx Employee
Xilinx Employee
379 Views
Registered: ‎11-05-2019

Hello @ysjung 

If you mean ILA, then System ILA is very useful.

Untitled.png

UG908 - Vivado Design Suite User Guide: Programming and Debugging (v2019.2)

Thank you
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katsuki
Xilinx Employee
Xilinx Employee
300 Views
Registered: ‎11-05-2019

 

Hi @ysjung 

 

If already issue has resolved, please Give Kudo or Mark the Answer as Accept as Solution and close this thread.

If you have any questions, you can post them.

 

Thank you.


Don’t forget to reply, kudo, and accept as solution. If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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