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cfgmgr2
Contributor
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Registered: ‎10-04-2018

Why is Microblaze C_INTERRUPT_IS_EDGE read-only?

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In Vivado (2019.1) IP integrator, in the advanced tab "Interrupt & Reset", the interrupt settings for Microblaze are greyed out.  Why is this?

Furthermore, if I try to manually set the sensitivity to "edge" via tcl command line, I get the following error:

>>set_property CONFIG.C_INTERRUPT_IS_EDGE 1 [get_bd_cells /microblaze_0]

>>CRITICAL WARNING: [BD 41-737] Cannot set the parameter C_INTERRUPT_IS_EDGE on /microblaze_0. It is read-only.

So how does one go about changing the Microblaze interrupt sensitivity to be "edge sensitive"?

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stephenm
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Registered: ‎09-12-2007

Yes, in the scenario you described the Microblaze sensitivity will be set to the default if there is no info passed to it in the pin properties.

For example, here is the BD of the setup you descibed:

bd.PNG

The Port prop is seen here:

port_prop.PNG

Since there is no port property on the GPIO pin here, then the default will be used.

 

If you are suing a custom IP here (and not the GPIO), then you could change the pin properties to make it type intr

and set the senstivity as you want.

 

Or, you could just add an external property (right click on the ipi canvas and select create port), and loop this in the RTL wrapper to your GPIO pin.

For example:

I made the senstivity of the external port rising edge:

create_port.PNG

 

I then connected this as shwon below:

bd_updated.PNG

If I then validate this, I see the pin property updated:

port_prop_updated.PNG

 

You would need to hook the signal in your top level wrapper

 

 

 

 

 

 

 

 

 

 

 

 

 

 

View solution in original post

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stephenm
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Registered: ‎09-12-2007

The sensitivity of the pin, would be derived by the master pin driving it.

 

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drjohnsmith
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Registered: ‎07-09-2009
@stephenm , how would one change the master pin to be edge or level sensitive ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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stephenm
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Registered: ‎09-12-2007

What are you connecting to the Microblaze interrupt? If this is a Interrupt controller, then you can do this in the IP configuration in Vivado IPI. If this is anyother pin, then then you can highlight the pin and do this in the pin properties

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cfgmgr2
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Registered: ‎10-04-2018

As an example, let's say I connect an AXI GPIO output to the interrupt input of a Microblaze. For this simple exercise, I am not using an interrupt controller with the Microblaze.  When I transition the GPIO output from low to high (e.g. from the PS), I'd like to cause one (and only one) interrupt to the Microblaze.  Obviously, this scenario can only work correctly if I can set the Microblaze's interrupt sensitivity to "edge-sensitive" - unfortunately I have not figured out how to do that, since the "C_INTERRUPT_IS_EDGE" property of the interrupt is read-only.

Is the only solution to always have to include an interrupt controller?  Surely there must be simpler way?

cfgmgr2
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Registered: ‎10-04-2018
... anyone?
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stephenm
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Moderator
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Registered: ‎09-12-2007

Yes, in the scenario you described the Microblaze sensitivity will be set to the default if there is no info passed to it in the pin properties.

For example, here is the BD of the setup you descibed:

bd.PNG

The Port prop is seen here:

port_prop.PNG

Since there is no port property on the GPIO pin here, then the default will be used.

 

If you are suing a custom IP here (and not the GPIO), then you could change the pin properties to make it type intr

and set the senstivity as you want.

 

Or, you could just add an external property (right click on the ipi canvas and select create port), and loop this in the RTL wrapper to your GPIO pin.

For example:

I made the senstivity of the external port rising edge:

create_port.PNG

 

I then connected this as shwon below:

bd_updated.PNG

If I then validate this, I see the pin property updated:

port_prop_updated.PNG

 

You would need to hook the signal in your top level wrapper

 

 

 

 

 

 

 

 

 

 

 

 

 

 

View solution in original post

cfgmgr2
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Contributor
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Registered: ‎10-04-2018
I think I follow your logic here.
Sorry for the newbie question, but how then do I hook the signal in the top-level wrapper? I can see that when I create the HDL wrapper, I presume I'll want to choose "Copy generated wrapper to allow user edits", but once inside the VHDL code, how do hook the I hook the gpio output to the microblaze IRQ input? I tried the following but I get a syntax error ("can't update in object mb_interrupt", cannot "read from out object gpio_io_o(0)").


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity design_1_wrapper is
port (
diff_clock_rtl_clk_n : in STD_LOGIC;
diff_clock_rtl_clk_p : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 );
mb_interrupt : in STD_LOGIC;
reset_rtl : in STD_LOGIC
);
end design_1_wrapper;

architecture STRUCTURE of design_1_wrapper is
component design_1 is
port (
diff_clock_rtl_clk_n : in STD_LOGIC;
diff_clock_rtl_clk_p : in STD_LOGIC;
reset_rtl : in STD_LOGIC;
mb_interrupt : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component design_1;
begin
design_1_i: component design_1
port map (
diff_clock_rtl_clk_n => diff_clock_rtl_clk_n,
diff_clock_rtl_clk_p => diff_clock_rtl_clk_p,
gpio_io_o(0) => gpio_io_o(0),
mb_interrupt => mb_interrupt,
reset_rtl => reset_rtl
);

--- added the following to try to hook gpio to mb irq input port
process begin
mb_interrupt <= gpio_io_o(0);
end process;

end STRUCTURE;
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stephenm
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Registered: ‎09-12-2007

I wouldn't update the wrapper directly as this will be updated automatically every time your generate the output products.

 

You can create a top rtl wi the the wrapper added (just copy and paste the wrapper here and change top level name). 

To look the input to output you need to create an internal signal, and connect this internal signal to input and output.

 

I'll send an example on Monday. 

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cfgmgr2
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Contributor
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Registered: ‎10-04-2018

Thanks!  Your replies are much appreciated.  I'll look forward to Monday.

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stephenm
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Registered: ‎09-12-2007

I have created a top level RTL, and instanciated the wrapper created by the block design. I have created an internal signal to loop the interrupt:

top.PNG

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cfgmgr2
Contributor
Contributor
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Registered: ‎10-04-2018

Thanks Stephen!

It works perfectly.  I truly appreciate the time you took to help and explain.