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Visitor
Visitor
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Registered: ‎01-22-2019

XAPP1079 at Vivado/XSDK 2018.3

Hi all, 

I've been trying to test XAAP1079 at Vivado 2018.3.

My results may be summed-up as follows:

  1. In debug, and when the board (Enclustra Mars ZX3) has been flashed with a XAAP1079 code generated from Vivado/XSDK 2014.2, compiled code in Vivado/XSDK 2018.3 works properly in debug mode. ARM0 starts ARM1 and the last one executes its code properly. All works fine.
  2. If this code is flashed, generating the .mcs file, ARM0 starts properly, but ARM1 remains stalled all the time. There is no response or action from this CPU (I'm using two leds to know if the processor is running or not).
  3. If i try to load the Vivado/XDSK 2018.3 compiled code in debug mode again, results are as in 2 case, and i have to load the code which has been generated at Vivado/XSDK 2014.2 in order to run the code in debug again.

I've read https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842203/Unsupervised+AMP, and https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842504/XAPP1079+Latest+Information but i didn't find anything that works for me...

I'm also trying to migrate to OpenAMP and Libmetal as shown in UG1189 and at https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841668/Multi-OS+Support+AMP+Hypervisor#Multi-OSSupport(AMP&Hypervisor)-Bare-metal/Bare-metalAMP but it was impossible for me to run a code... 

If more information are require, i will provide it.

Thanks in advance,

Victor.

 

 

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Xilinx Employee
Xilinx Employee
1,717 Views
Registered: ‎09-01-2014

I think you need to debug it.
You can enable FSBL_DEBUG_INFO flag in FSBL to check if CPU0 and CPU1 APPs are loaded to the correct memory location.
Then you can check if CPU1 starting address is written correctly to the 0xFFFFFFF0 by CPU0 and SEV is issued either.
Since you mention CPU1 doesn’t work, you can check the PC of CPU1 to see it was still in a wait loop or stuck is somewhere else.

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Visitor
Visitor
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Registered: ‎01-22-2019

Hi Ritakur, 

Thanks for your response. I will try to debug FSBL as you say. I'm trending to think that the issue is in FSBL, due to I'm using the standard ones which are generated with vivado, and not a modified version of them as describes XAPP1079. I thought that DUSE_AMP=1 flag will allow the compiler to compile the code which was able to manage more than one partition... but guess i was wrong.

Are there any new revision of the XAPP 1079 application nothe where this files are available for downloading, or any kind of documentation where this process had been explained?

Best regards,

Victor.

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎09-01-2014

There is no new version of the xapp1079.
Since you use the latest version of FSBL, you don’t need to modify it. It will load all the apps from bootimage to memory. xapp1079 is a simple design, all the flow is documented clearly.
DUSE_AMP=1 is only used for CPU1 app to prevent reinitializing the common module.
FSBL and CPU0 app should not use it.
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Visitor
Visitor
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Registered: ‎01-22-2019

It is exactly what i did... I use the FSBL which are generated with Vivado, and use the flag DUSE_AMP=1 at CPU1 BSP.

In order to provide more information, I'm going to insert my the code here:

For ARM0:

void init_CPU1(void)
{
    u32 RegVal;
    //Disable cache on OCM
    Xil_SetTlbAttributes(0xFFFF0000, 0x14de2);

    //Disable cache on fsbl vector table location
    Xil_SetTlbAttributes(0x00000000, 0x14de2);

    Xil_Out32(CPU1_CATCH, APP_CPU1_ADDR);

	Xil_Out32(XSLCR_UNLOCK_ADDR, XSLCR_UNLOCK_CODE);
	// Assert and deassert cpu1 reset and clkstop using above sequence
	RegVal = Xil_In32(A9_CPU_RST_CTRL);
	RegVal |= A9_RST1_MASK;
	Xil_Out32(A9_CPU_RST_CTRL, RegVal);
	RegVal |= A9_CLKSTOP1_MASK;
	Xil_Out32(A9_CPU_RST_CTRL, RegVal);
	RegVal &= ~A9_RST1_MASK;
	Xil_Out32(A9_CPU_RST_CTRL, RegVal);
	RegVal &= ~A9_CLKSTOP1_MASK;
	Xil_Out32(A9_CPU_RST_CTRL, RegVal);

	// lock the slcr register access
	Xil_Out32(XSLCR_LOCK_ADDR, XSLCR_LOCK_CODE);

	CONTROL_FLAG_ARM0 = 0;
}

And for ARM1:

void init_sharedMemorySegment_FROM1()
{
	Xil_SetTlbAttributes(SHARED_MEMORY_START_ADDRESS,0x14de2);
	sleep(2);

	//xil_printf("DEBUG - AAPv1b - ARM1 - Processor online without debug support\r\n");
}

void wakeUp_System()
{
	while(CONTROL_FLAG_ARM0 == 0){};

	CONTROL_FLAG_ARM0 = 0;

	//xil_printf("ARM1 - Processor started and online\r\n");

	//return XST_SUCCESS;
}

This code is as appear for XAPP 1079.

I use BSP standalone v6.8, which theoretically includes AMP support. AMP flag is asserted for ARM1:

-mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -nostartfiles -g -Wall -Wextra -DUSE_AMP=1

The flash file (.mcs) is generated using the "Create Boot Image" widget:Captura.PNG

Previous image is the actual image I'm generating.

If you were so kind as to have a look at the code and generation and give me feedback about something strange or wrong i'll be so grateful...

Thanks for all your support.

 

 

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