XC7Z010 - can I automatically invalidate cache with my PL to DDR writes?

[akohlsmith2]

I'm running Linux to process video data from DDR. The video data is written to DDR via the PL, which uses the four AXI_HP ports to write this video data to DDR.

Is it possible to write to DDR from PL (using the four AXI_HP ports) and have the L1/L2 cache invalidate any lines that might contain data from the area written through AXI_HP? I am aware of the ACP, but this is a MUCH slower interface than four AXI_HP ports. I am aware of the AxCACHE bits on the AXI transfer, but those only determine policy for the AXI transfer and I cannot find anything in the TRM which states that writes on AXI_HP can invalidate or notify the SCU that it might now have stale data.

It seems the generic answer here is to disable cache entirely, which is not a real answer, it's like saying to take the wheels off your car to ensure you never go above 100km/hr.

If it is not possible to have the PL directly notify the SCU, is there a Linux kernel call which can invalidate cache for a region of RAM? I don't want to disable cache entirely and I would very much prefer not to invalidate the entire L1/L2 cache.

[muzaffer]

the fact that hpx ports are not coherent means there is no automatic way for the writes through them to invalidate cache. The solution is to use dma_sync_single_for_cpu and dma_sync_single_for_device to manage buffer ownership in the kernel driver (ie when you get the video interrupt, do the first, and when the cpu is done with the buffer so another frame can be copied into it, do the latter)

[horacioneto]

I am doing something similar to yours but with only 1 AXI_HP port.

My solution was to reserve a memory range in the DDR for the video data, in order for the Linux not to use it. This is done is bootargs by using MEM=256M for instance, saying Linux can only use the first 256M of DDR. The other 256M will not be cached.

If you access multiple times to such non-cached data, it is better to copy such data to a local variable. Such variable will be located in your heap, and hence, in the memory range in the DDR that Linux has access, thus being cached.

Although this don't answer to your question, it solved a similar problem that I had. Hope it helps you :)