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Observer
Observer
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Registered: ‎09-05-2018

Z7030 EMAC Will not Tx between debug sessions without a hard reset

Hi,

I've encountered a few problems with our EMAC driver on both Ultrascale 3EG and Zynq 7030.

 

I'm trying to re-visit a problem that I can desribe in the following steps.

 

1. Have a Z7030 Vivado project with EMAC setup, connected to a TI DP83867 PHY + 100Mb Link to HUB. 

2. Create a LWIP Echo Server project in SDK, put a breakpoint on or about line 353 in xemacpsif_dma.c (LWIP Port Folder)

3. Do a fresh power on reset of the hardware, don't worry about any Bitstream.

4. Debug the LWIP Project, it should send a Gratutious ARP when the EMAC is up

5. Observe either the ARP (Reply) in Wireshark, or monitor the Zynq -> PHY Tx_EN pin with a scope to observe the transmit was generated.

6. Terminate the debug session, and reload the same application, DO NOT power cycle the hardware.

7. Repeat step 4.

8. Observe you DO NOT get any Tx_EN signal from the Zynq, and you obviously get no packet on the wire.

 

My feeling here is that either using my own EMAC driver, or the LWIP "out of the box code" produces the same result, is there may some errata for the GEM in the Z7030 that would cause this behaviour?

 

Thanks.

 

 

 

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