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Visitor
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Registered: ‎08-06-2020

ZYNQ AXI master port

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Hi all,

in my block design I connectd with an AXI Interconnect the AXI master port of my ZYNQ, that is M_AXI_GP0, with the AXI slave port S00_AXI of an AXI slave created making use of  "Tools/Create and PAckage new IP". I started by a data width of 32 bit and it is ok, but now I modify my AXI slave to write and read 64-bit data (C_S00_AXI_DATA_WIDTH : integer := 64).

My question is: how can I do to change data size at my PS side?

I thought it was simple, but can't find an AXI master port with 64 data with, that seems a little strange... Otherwise, can you suggest me some workaround?

 

Thanks a lot in advance.

 

Alessandra

 

 

 

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Moderator
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Registered: ‎11-09-2015

HI @ale11286 

Refer to the Zynq-7000 TRM (UG585).  The M_AXI_GP ports are General Purpose 32-bit AXI Master.

So you cannot change its data width

The workaround would be to use an AXI interconnect to do the connection between the 32-bit interface of the zynq and the 64-bit interface of your IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
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Registered: ‎11-09-2015

HI @ale11286 

Refer to the Zynq-7000 TRM (UG585).  The M_AXI_GP ports are General Purpose 32-bit AXI Master.

So you cannot change its data width

The workaround would be to use an AXI interconnect to do the connection between the 32-bit interface of the zynq and the 64-bit interface of your IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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