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shyam457
Adventurer
Adventurer
4,876 Views
Registered: ‎01-26-2015

ZYNQ ZC702 PS and PL timing - writing to Custom IP port

Hi,
I am working on a project involving both the PS and PL sections of zynq zc702.
I have created my own custom IP. But the problem is I can't seem to get the timing right.
Is there any way to wait or keep in hold the processing of both PL and PS till the value in my custom IP output port is updated??

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4 Replies
balkris
Xilinx Employee
Xilinx Employee
4,871 Views
Registered: ‎08-01-2008

i think you can use interrupts
http://www.xilinx.com/support/answers/62107.html
http://www.xilinx.com/support/answers/62107.html
http://www.xilinx.com/support/documentation/user_guides/ug821-zynq-7000-swdev.pdf
Thanks and Regards
Balkrishan
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shyam457
Adventurer
Adventurer
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Registered: ‎01-26-2015

Thanks. But could you tell me how using interrupts would solve this timing problem?? I do not understand it
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muzaffer
Teacher
Teacher
4,839 Views
Registered: ‎03-31-2012

what does your IP's interface to PS look like?
The easiest is to make an axi-lite port to which the PS can write to start processing (after writing data maybe) and then loop on a bit in the register address-space to see if the IP has completed processing. If you don't want to loop, you can also make the IP create an interrupt to signal completion.
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shyam457
Adventurer
Adventurer
4,834 Views
Registered: ‎01-26-2015

I am using axi lite port. i am using 1 port to write data to IP from PS, 1 port to send a signal to ip to start processing and another port from PL to ps to indicate ip has finished processing.I also have used 2 o/p ports to get o/p from PL to PS
I have mapped these ports to the axi slave registers to make it accessible from PS as well.
But the timing does not come out right.
For example when 1 of my o/p ports is to be FFFFFFFF; when I try to print out the value in that slave register, it comes up as 111EEFF..hen 111FEF ..EF11FF and so forth??
Won't the ports and slave registers update their values simultaneously?? Is that the problem??
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