Using 2016.2 with ZynQ 7z045.
Have configured the Master AXI interface 0 in the ZynQ7 Processing System. However, there is something I'm not clear on. on Page 142 Section 5.6.2 of the TRM it states
"All clocks must be active and all resets must be inactive on all PS-PL AXI interfaces for the GPV tofunction properly. The entire PS might hang if this condition is not satisfied ..."
Now for the M_AXI_GP0_ACLK what is the source for this clock? Can it be the FCLK_CLK0 the ZynQ7 Processing System? Is it a PL clock from a MMCM/PLL?
if it is the later what is the mechansim to ensure the PL clock source is locked? i.e how do we read the locked signal
For M_AXI_GP0_ACLK FCLK can be the source.