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Zynq-7000 SoC ZC706 Clocking Resources

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Hi,

I am looking for clocking resources for Zynq-7000 SoC ZC706 Evaluation Kit.

I found one for 7 Series https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf 

Not sure if both the family share similar clocking architecture. Is there any documentation specific for Zynq-7000 SoC ZC706?

Thank you.

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Registered: ‎01-22-2015

@karan_gadhia 

In short, UG954 lists clock sources found on the ZC706 board that the XC7Z045-2FFG900C FPGA can use.  Some of these sources are routed to the PS-side of the FPGA and some are routed to the PL-side of the FPGA.  UG472 shows what to do with the source clocks for the PL-side once they enter the FPGA.

All the ZC706 clock sources are listed in Table 1-12 of UG954.  Clock sources for the PL-side are:

1) System Clock (U64):  This is a fixed-frequency (200MHz) clock, intended for use as the main clock input to the PL-side.  It is routed from IC, U64, across the board to clock-capable input pins, (G9, H9), on the FPGA.  From these FPGA pins, the clock is typically routed through the FPGA to a clock management tile (CMT) block called the MMCM which is described in Chapter 3 of UG472.  The MMCM can be configured using the Vivado Clocking Wizard (see Xilinx document PG065) to produce other clocks inside the FPGA that are needed for your design and to route them throughout the FPGA.

2) User Clock (U37):  This is a user-programmable clock intended for general purpose use.  It is routed from IC, U37, across the board to clock-capable input pins, (AG14, AH14), on the FPGA.  From these FPGA pins, the clock is typically routed to an MMCM inside the FPGA.

3) User SMA Clock:  This is a pair of SMA connectors, (J67, J68),  that can be connected to a user-provided off-board differential-clock source.  From these connectors, the clock is routed across the board to clock-capable input pins, (AD18, AD19), on the FPGA.  From these FPGA pins, the clock is typically routed to an MMCM inside the FPGA.

4) GTX SMA Clock:  This is a pair of SMA connectors, (J36, J31),  that can be connected to a user-provided off-board differential-clock source.  From these  connectors, the clock is routed across the board to clock-capable input pins, (W8, W7), on the FPGA.  This is a special purpose clock used by the GTX/GTH Transceivers (see UG476) in the FPGA.  These transceivers are used for high-speed communication (up to 12.5 Gb/s) with the FPGA.

5) Jitter Attenuated Clock (U60):  As described in UG954, this is a special purpose clock that is used primarily by the FPGA GTX/GTH Transceivers (see UG476).

Cheers,
Mark

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Moderator
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Registered: ‎06-14-2010

Hello @karan_gadhia ,

Can you check this user guide 585 (https://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf) and the Clocking is explained in detail in Chapter 25. Is this what you are looking for?

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Visitor
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Registered: ‎06-12-2019

Hi @anatoli 

Thank you for replying. I did looked into the technical reference manual but it describes PS side clocks in details and I am interested in the PL side. Its from this document I came to know that for PL clocks I have to refer to 7 series FPGAs clocking documentation. The problem is that I cannot correlate 7 series clocks with clocks mentioned in ZC706 Eval guide 

If there is any document that explains this correlation wrt to clocks mentioned in Eval guide that will be great for me to understand. I have started looking into the 7 series clocking resources and try to understand it.

Thank you.

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-21-2018

Hi Karan,

Yes, Zynq-7000 uses 7 series clocking resources. 

I found these Xilinx slides that are now part of a college course that are helpful (slides 26-28):
http://www.ioe.nchu.edu.tw/Pic/CourseItem/4468_20_Zynq_Architecture.pdf

Let us know if you have questions.

Thanks,
Andres

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Registered: ‎01-22-2015

@karan_gadhia 

In short, UG954 lists clock sources found on the ZC706 board that the XC7Z045-2FFG900C FPGA can use.  Some of these sources are routed to the PS-side of the FPGA and some are routed to the PL-side of the FPGA.  UG472 shows what to do with the source clocks for the PL-side once they enter the FPGA.

All the ZC706 clock sources are listed in Table 1-12 of UG954.  Clock sources for the PL-side are:

1) System Clock (U64):  This is a fixed-frequency (200MHz) clock, intended for use as the main clock input to the PL-side.  It is routed from IC, U64, across the board to clock-capable input pins, (G9, H9), on the FPGA.  From these FPGA pins, the clock is typically routed through the FPGA to a clock management tile (CMT) block called the MMCM which is described in Chapter 3 of UG472.  The MMCM can be configured using the Vivado Clocking Wizard (see Xilinx document PG065) to produce other clocks inside the FPGA that are needed for your design and to route them throughout the FPGA.

2) User Clock (U37):  This is a user-programmable clock intended for general purpose use.  It is routed from IC, U37, across the board to clock-capable input pins, (AG14, AH14), on the FPGA.  From these FPGA pins, the clock is typically routed to an MMCM inside the FPGA.

3) User SMA Clock:  This is a pair of SMA connectors, (J67, J68),  that can be connected to a user-provided off-board differential-clock source.  From these connectors, the clock is routed across the board to clock-capable input pins, (AD18, AD19), on the FPGA.  From these FPGA pins, the clock is typically routed to an MMCM inside the FPGA.

4) GTX SMA Clock:  This is a pair of SMA connectors, (J36, J31),  that can be connected to a user-provided off-board differential-clock source.  From these  connectors, the clock is routed across the board to clock-capable input pins, (W8, W7), on the FPGA.  This is a special purpose clock used by the GTX/GTH Transceivers (see UG476) in the FPGA.  These transceivers are used for high-speed communication (up to 12.5 Gb/s) with the FPGA.

5) Jitter Attenuated Clock (U60):  As described in UG954, this is a special purpose clock that is used primarily by the FPGA GTX/GTH Transceivers (see UG476).

Cheers,
Mark

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@andresb 

Hi Andres,

Thank you for sharing the slides.

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markg@prosensing.com 

Hi Mark,

Thank you for summarizing the clocking scheme. After playing around with the clocking wizard IP on vivado and referning to UG768 I had a better understanding of using the clocks on PL side. 

Thank you.

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Registered: ‎01-22-2015

@karan_gadhia 

You are very welcome.

Please be aware that UG768 is for use with the ISE development tools.  Although ISE supports the Zynq-7000, Xilinx recommends that you instead use the Vivado development tools for working with the Zynq-7000.  If you are using Vivado, then you should also be using UG953 instead of UG768.

Cheers,
Mark

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Thanks markg@prosensing.com for pointing that out. 

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