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Registered: ‎03-26-2019

Zynq-7000 Virtual FIFO Error


we are using a MicroZed Development Board (Zynq 7000, 1Gb DDR3 SDRAM) to transfer data via AXI from PL to PS. In essence, a custom IP core receives data from an external ADC (SPI interface), forwards them to another custom IP core which converts the data to AXI and from there, the data is fed into an AXI Virtual FIFO Controller. Afterwards, the Linux running on the PS reads the data via DMA from the FIFO.

The block design looks as following:

Block DesignBlock Design

Sometimes the design runs just fine. We can verify that the PS reads the correct data from the FIFO. However, sometimes (like every second time we reset and reboot the system), a strange error occurs: it seems like the FIFO gets full immediately after boot and subsequently, the Xilinx DMA kernel module throws a lot of errors of the same type:

xilinx-vdma 7fff800.dma: Channel ef153610 has errors 10, cdr 0 tdr 0

Re-running the synthesis sometimes produces better builds (that is, the error occurs like every fifth time), sometimes the build doesn't work at all and we always get the error message. Timing constraints are met, no critical warnings are shown during synthesis. Vivado versions 2018.2 and 2019.1 were both tested and deliver the same results.

Our current assumption is that somehow, the Virtual FIFO IP core is broken; for example, we observed that the reset does not work correctly, that is, it does not flush the FIFO. In case it's relevant, I also attached the FIFO configuration:

VFIFO ConfigVFIFO Config

Unfortunately, searching the web did not yield any solutions. Does anyone know how to further investigate the issue or can propose an alternative design?

Thanks in advance!

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2 Replies
Xilinx Employee
Xilinx Employee
Registered: ‎10-04-2016

Hi @heerdominique ,

AXI DMA is throwing a DMAIntErr. It looks like you are using AXI DMA in simple mode (not scatter gather), so this indicates that the incoming stream packet is bigger than what is in the DMA length register.

There are a few things about your design that concern me.

1. How are you managing memory so that the Virtual FIFO and the Linux operating system don't collide? Are you using reserved memory for the Virtual FIFO region?

2. Why is the read channel enabled on your AXI DMA? It doesn't appear you are using it.

3. Why is the FIFO going full immediately after boot? Is the ADC already sending data? Or is there an issue in the reset/start up sequence? 

I never see Zynq designs that use the Virtual FIFO IP. It doesn't make sense to shove the stream data into DRAM with the Virtual FIFO and then pull it back out to move it to another location in DRAM with AXI DMA. Consider removing the Virtual FIFO and use the AXI DMA with scatter gather to write your data to DRAM once. You will need to make sure that AXI DMA is always available to transfer data into DRAM by keeping it supplied with buffer descriptors. If necessary, you could add an AXI Stream FIFO if there is backpressure on the ADC.




Don’t forget to reply, kudo, and accept as solution.
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Registered: ‎03-26-2019

Hi @demarco,

thanks a lot for your repsonse! To answer your questions:

1. Yes, we are using a reserved region for the VFIFO core.

2. Thanks for pointing that out, indeed we don't use the read channel.

3. The ADC is always sending data, but we made sure the data only reaches the FIFO after the system is booted / ready.

Based on your remarks, we decided to try another approach without the Virtual FIFO and use the DMA Core in Scatter Gather Mode. Thanks again for your response, I'll keep you posted.


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