How do I check the status of the caches on the Zynq 7020? Specifically I want to know:
- What's the current L1/L2 cache configuration
- What's currently in the L1 caches (and are they dirty?)
- What's currently in the L2 cache (and are they dirty?)
I was expecting to find cache control/status registers, but I'm not seeing anything that looks like what I expect...
Hi @ckemsley ,
Are you looking at the contents of the Cache Type Register in the A9 processor registers to determine the cache configuration?
I don't believe it is possible to read the cache tag RAM via processor registers.
For all of your questions, you will need to consult the Arm v7-A Architecture Reference Manual for details. This document is available for download from infocenter.arm.com.