12-21-2012 09:45 AM
Yes, we have such designs but none are ready to be shared as demo's or examples. Contact your distributor or Xilinx FAE for more information and help with the ACP. There is much in the way of development going on to support the HLS (high level synthesis).
01-09-2013 07:13 AM
Thanks. While waiting I found this design.
But there doesnt seem to be a event wire connection made to the ARM from the PL (CDMA in this example) as explained below.
So Is the above design running non-polled/interuppet mode? Seems strange though as it differs from the description above.
01-29-2013 03:21 AM
I have created a sample design in which I have an AXI master residing on the ACP port,
through which I have been able to perform coherent read/write transactions to the
both the Memory Area and also to OCM.
The design contains also required firmware and driver for memory allocation, interrupt handling,
and other required tasks.
May be if needed I can share the design (hardware and software) along with suitable descriptions
through a suitable mean with other people.
U of Bologna, italy.
01-29-2013 07:12 AM
Posting your design on zedboard.org forums or here might be a really nice thing to do.
And, I would be pleased if you would email it to me?
09-13-2013 01:52 PM
Here is the complete description of our tests on the ACP port of the ZYNQ device.
complete source code is also available. For that, please write me. (my offical email address).
10-10-2013 11:00 PM
You can look at the following application note. Even though the XAPP makes use of Vivado HLS to create the IP, the basic procedure to interface an IP with the ACP port remains the same.
10-15-2013 04:48 AM
i am trying to connect a simple hardware module to the acp port and write simply some data into the cache to be read by the cpu. I have tried many different possibilities using stream AXI4 because of the burst capabilities and the capacity of sending data with higher frequency. Is there any documentation regarding how exactly to write the data into the cache and read it with the cpu?
Right now I am only using a custom IP with AXI4 stream connected to an AXI interconnect and this goes directly to the ACP. Can this work like this? Or would I need a DMA Module?
Thank you very much for your help.
10-11-2018 07:36 AM
Thanks for sharing your work in the community. Is the design source codes of the work presented in this paper is open source and accessible by other designers to get some insighs in their own way?
Thsnks and Regards,