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Adventurer
Adventurer
15,576 Views
Registered: ‎10-24-2007

Zynq ACP (accelerator coherency port)

Hi all,

Is there any reference designs for accelerator coherency port in the Zynq.

Thanks.

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Scholar
Scholar
15,569 Views
Registered: ‎02-27-2008

c,


Yes, we have such designs but none are ready to be shared as demo's or examples.  Contact your distributor or Xilinx FAE for more information and help with the ACP.  There is much in the way of development going on to support the HLS (high level synthesis).

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
15,527 Views
Registered: ‎10-24-2007

We are an university under the of Xilinx University Program and we dont have direct FAE. Who can I connect in Xilinx about this for XUP.

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Scholar
Scholar
15,516 Views
Registered: ‎02-27-2008

c,

 

Your professor has the contacts for the XUP.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
15,493 Views
Registered: ‎10-24-2007

Thanks. While waiting I found this design.

http://www.xilinx.com/support/answers/50826.htm

 

But there doesnt seem to be a event wire connection made to the ARM from the PL (CDMA in this example) as explained below.

http://www.em.avnet.com/en-us/design/trainingandevents/Documents/X-FEST%202012%20PRESENTATIONS/xfest12_pdf_zynq_accel_v1_2_may30.pdf (page 44,53)

 

So Is the above design running non-polled/interuppet mode? Seems strange though as it differs from the description above.

 

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Explorer
Explorer
15,409 Views
Registered: ‎09-19-2010

Hi, 

 

I have created a sample design in which I have an AXI master residing on the ACP port, 

through which I have been able to perform coherent read/write transactions to the 

both the Memory Area and also to OCM. 

 

The design contains also required firmware and driver for memory allocation, interrupt handling, 

and other required tasks. 

 

May be if needed I can share the design (hardware and software) along with suitable descriptions 

through a suitable mean with other people. 

 

Thanks, 

M.S. Sadri,

U of Bologna, italy. 

 
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Scholar
Scholar
15,402 Views
Registered: ‎02-27-2008

m,

 

Posting your design on zedboard.org forums or here might be a really nice thing to do.


And, I would be pleased if you would email it to me?

 

austin@xilinx.com

Austin Lesea
Principal Engineer
Xilinx San Jose
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Explorer
Explorer
15,344 Views
Registered: ‎12-05-2012

Hello M.S. Sadri,
Can you mail me your design to my email ID: pruthvirocks@gmail.com

with regards
Pruthvi
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Explorer
Explorer
14,357 Views
Registered: ‎09-19-2010

Hi

 

Here is the complete description of our tests on the ACP port of the ZYNQ device. 

 

http://www.googoolia.com/downloads/papers/sadri_fpgaworld_ver2.pdf

 

complete source code is also available. For that, please write me. (my offical email address).

 

Regards.

Mohammad.

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Scholar
Scholar
14,210 Views
Registered: ‎09-05-2011

Hi,

 

You can look at the following application note. Even though the XAPP makes use of Vivado HLS to create the IP, the basic procedure to interface an IP with the ACP port remains the same.

 

http://www.xilinx.com/support/documentation/application_notes/xapp1170-zynq-hls.pdf

 

Regards,

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Newbie
Newbie
4,991 Views
Registered: ‎10-15-2013

Dear all,

 

i am trying to connect a simple hardware module to the acp port and write simply some data into the cache to be read by the cpu. I have tried many different possibilities using stream AXI4 because of the burst capabilities and the capacity of sending data with higher frequency. Is there any documentation regarding how exactly to write the data into the cache and read it with the cpu? 

 

Right now I am only using a custom IP with AXI4 stream connected to an AXI interconnect and this goes directly to the ACP. Can this work like this? Or would I need a DMA Module?

 

Thank you very much for your help.

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Adventurer
Adventurer
2,874 Views
Registered: ‎08-30-2018

Hi @mamisadegh3,

 

Thanks for sharing your work in the community. Is the design source codes of the work presented in this paper is open source and accessible by other designers to get some insighs in their own way?

 

Thsnks and Regards,

Daryon,