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Newbie
Newbie
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Registered: ‎06-06-2018

Zynq AXI DMA interrupts on CPU1

Hi All,

 

Our application currently runs under FreeRTOS and facilitates DMA data transfers PL-PS without any issues on CPU0. As part of application performance optimisation we would like to do DMA operations on CPU1. After porting the functionality to the second core which runs the second instance of FreeRTOS we haven't managed to make it work the same way as it is on the first core. A particular interrupt ID has been retargeted to CPU1 only, our interrupt handler is hit, however, attempts to invoke XAxiDma_BdRingFromHw give 0 suggesting that there is no data available.

 

What is the fundamental difference of running the same code capable of DMA transfers on different CPU cores?

 

Thank you in advance,

Dmitry

http://magictale.com - DIY Kits, Entertaining Projects, Hacks and Reviews
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Contributor
Contributor
631 Views
Registered: ‎04-04-2018

Re: Zynq AXI DMA interrupts on CPU1

Hi Dimitri,

 

> attempts to invoke XAxiDma_BdRingFromHw give 0

> suggesting that there is no data available.

 

When multiprocessing, the behavior you describe is frequently due to cache & interrupt distributor issues. Looks like you're gtg with the latter. The driver should (and does) attempt to invalidate before accessing the bd in BdRingFromHw ... but it wouldn't hurt to double-check. You can always nail up some non-cacheable memory for the bds/buffers to confirm any suspicions.

 

 

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