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boeck
Contributor
Contributor
9,182 Views
Registered: ‎09-25-2008

Zynq AXI Datamover HP0 Problem

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Hi,

 

I implemented my own DMA core by connecting the Datamover 4.02a to the HP0 Port of the Zynq. I only use the mm2s interface of the datamover to read data from the DDR and receive data on the AXI streaming interface.

 

Everything works well when the PS configures the PL after power up.

But the following scenario generates a strange behaviour:

 

After Power up, the PS configures the PL and writes, only once, Data into the DDR.

My own DMA core reads continuously data from the DDR via AXI HP0. Everything works fine.

For further development, i connencted the JTAG cable to the Zynq and configure the PL with JTAG during operation, but this shows a strange behaviour on the HP0 AXI Bus.

 

It seems that there remains old Data from a previous AXI transfer on the AXI bus. And the first few transfers deliver wrong data after reconfiguration via JTAG. Although I read from the same address. I also connected chipscope to see the details.

 

In screenshot axi_datamover_1.png the first transfer after reconfiguration at Address 0x3B600000 (axi_datamover_0_s_axis_mm2s_cmd_tdata_o) can be seen. It delivers the data 0xAAFFFFFFAAFFFFFF which is old data from a previous transfer. The correct data should be 0xAA0000FFAA0000FF. With devmem command in linux the correct data can be read from this DDR address. When reading from the same address, after a few wrong transfers, the correct data is delivered again. What also can be seen in the PNG is, that the HP0 FIFO Control RCOUNT port is set to 0x5A directly after reconfiguration.

 

So this would also indicate, that there is old data stored in the HP0 Port of the Zynq. Allthough I disabled using FIFOs.

Is this a correct behaviour?

 

Is there a possibility to reset the HP0 Interface of the PS from the PL? Or is there a posibility to emptying the datapath of the HP0?

 

I hope someone can help me.

Many Thanks,

 

Best Regards,

Stefan

 

AXI_Datamover_1.png
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1 Solution

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dylan
Xilinx Employee
Xilinx Employee
11,013 Views
Registered: ‎07-30-2007

The PS AXI interfaces cannot be reset, and so the PL logic driving it should be idle before issuing a reconfiguration.

 

Dylan

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dylan
Xilinx Employee
Xilinx Employee
11,014 Views
Registered: ‎07-30-2007

The PS AXI interfaces cannot be reset, and so the PL logic driving it should be idle before issuing a reconfiguration.

 

Dylan

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boeck
Contributor
Contributor
9,155 Views
Registered: ‎09-25-2008

Hi Dylan,

 

Thanks for you fast reply. Ok I allready thought so, but I want to be sure not to miss something.

 

Stefan

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guillaumebres
Scholar
Scholar
8,366 Views
Registered: ‎03-27-2014

This is exactly what i would like to do,

could you tell me which AXi interface and protocol did you use inside your personnal IP to connect it to the Datamover?

gw.
Embedded Systems, DSP, cyber
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boeck
Contributor
Contributor
8,358 Views
Registered: ‎09-25-2008

I developed an core to read data from the DDR (HP0) and stream it to an Display.

 

So I use the following interfaces of the Datamover:

 

Data Interfaces:

 

M_AXI_MM2S: connected via an AXI interconnect to the HP0 port of the PS.

M_AXIS_MM2S: connected to my Display Controller Core

 

Control Interfaces:

 

M_AXIS_MM2S_CMD: Used in my DMA Core to control the DataMover Transfers

M_AXIS_MM2S_STS: Used in my DMA Core to get the Status of the DataMover Transfers

 

I hope this is the Information you need...

 

regards

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fradaric
Observer
Observer
7,372 Views
Registered: ‎05-29-2012

Hii boeck,

I need to use the DDR3 via HP0, for that I have developed a custom AXI interface(for DDR read and write). Since I am new in using Zynq board I didn't quite understand how to connect/configure the HP0 with my logic.  If you don't mind, could you please expalin how did you bring up the DDR3. 

Joe
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