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imgignacio
Explorer
Explorer
4,220 Views
Registered: ‎11-24-2013

Zynq MP Ethernet SGMII GT Transceivers

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Dear Forum,

 

is there any example of device tree for the Ethernet Phy when the GT transceivers are being used as phy (SGMII)?

 

I mean this configuration:

Selection_045.png

 

Unfortunately I cannot find any information about what the driver expects and I need to create a valid device tree with this configuration for ethernet on my board to work.

 

According to this AR, it should look like this:

https://www.xilinx.com/support/answers/66592.html

 

&gem2 {
        phy-handle = <&phy0>;
        phy-mode = "sgmii";
        phy0: phy@0{ <- is this always 0?
                reg = <0>; <- is this always 0?
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
        };
};

 

Also, what about the serdes? Must a line be added, like with USB3 or PCIe? Like this:

<&lane3 PHY_TYPE_SGMII 3 3 125000000>;

Thanks in advance!

Have a nice weekend!

 

Regards

Ignacio

 

 

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1 Solution

Accepted Solutions
pillinj1
Contributor
Contributor
5,015 Views
Registered: ‎02-11-2014

I had that same question as you for a long time. I did finally get it to work with the near exact device tree you had

 

&gem0 {
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "sgmii";
    phy0: phy@0{
        reg = <0>;
        ti,rx-internal-delay = <0x8>;
        ti,tx-internal-delay = <0xa>;
        ti,fifo-depth = <0x1>;
        ti,rxctrl-strap-worka;
    };
};

 

As you can see, there's no SERDES config line (in my case it would have been "phys = <&lane0 PHY_TYPE_SGMII 0 2 125000000>;")

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7 Replies
pillinj1
Contributor
Contributor
5,016 Views
Registered: ‎02-11-2014

I had that same question as you for a long time. I did finally get it to work with the near exact device tree you had

 

&gem0 {
    status = "okay";
    phy-handle = <&phy0>;
    phy-mode = "sgmii";
    phy0: phy@0{
        reg = <0>;
        ti,rx-internal-delay = <0x8>;
        ti,tx-internal-delay = <0xa>;
        ti,fifo-depth = <0x1>;
        ti,rxctrl-strap-worka;
    };
};

 

As you can see, there's no SERDES config line (in my case it would have been "phys = <&lane0 PHY_TYPE_SGMII 0 2 125000000>;")

View solution in original post

imgignacio
Explorer
Explorer
4,100 Views
Registered: ‎11-24-2013

Hi @pillinj1,

 

thanks a lot for your answer!

 

Regards

Ignacio

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imgignacio
Explorer
Explorer
4,053 Views
Registered: ‎11-24-2013

Hi @pillinj1,

 

may I ask you which PHY you were using? Did you have to do any modification on the FSBL for the GT transceivers to work?

 

I am triying this connecting to a switch with a SGMII integrated PHY. Linux says there's link and the TX packet counter shows a number with no errors. Nevertheless, the RX packet counter is always 0 and there's no way to send/receive any kind of packet.

 

Thanks in advance!

Regards,

Ignacio

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pillinj1
Contributor
Contributor
4,044 Views
Registered: ‎02-11-2014

I'm using GEM0 (so GTR0) and am bringing in the reference clock on GT Ref Clk 2. I did not have to make any manual modifications to the FSBL. I had it working with 2017.3 and 2017.4 FSBLs.

 

Edit: the phy was the same as the ZCU102 (TI DP83867) but wired for SGMII.

baruchlerer
Observer
Observer
3,428 Views
Registered: ‎05-10-2018

Hi I have the exact same issue, did you finally solved it, if so can you share how?

I'm using petalinux 2018.1

Many Thanks

Baruch

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stw-prepelica
Visitor
Visitor
1,388 Views
Registered: ‎10-28-2019

Hi!

have you solved it? I know, it's been a long time since your reply on this topic but maybe you could give me a hint?

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Acksam88
Observer
Observer
235 Views
Registered: ‎03-24-2021

Good day, i just wanna ask did u configure the PSU in vivado with the MDIO pins enabled?

i couldnt seem to get it working..

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