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Visitor
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2,766 Views
Registered: ‎10-13-2007

Zynq PL configuration in a DDRLess system

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Attempting to do this by

 

1. moving small chunks of bit stream data from QSPI Flash to OCM

2. XDcfg_Transfer from OCM to the PL

3. repeat until all data is transferred

 

Does not work. PS code is derived from the xdevcfg_polled_example.c

 

I can see the OCM buffer contain the correct data, and is aligned to 64K. The bytes have little endian alignment. The last DMA transfer has the two LSBs of source address set to “01”

 

The code from xdevcfg_polled_example.c is split into three parts:

 

a) initialization part (called once) consisting of

       XDcfg_LookupConfig, XDcfg_CfgInitialize, XDcfg_SelfTest and enable level shifters from PS to PL

 

b) DMA transfer part (called repeatedly) consisting of

       XDcfg_IntrClear, XDcfg_ReadReg, XDcfg_Transfer and XDcfg_IntrGetStatus to poll for DMA done

 

c) closing part consisting of

       polling for IXR_PCFG_DONE. this does not happen.

 

UG585 says “A single PCAP readback access cannot be split across multiple DMA accesses”

 

is this true for write as well?

 

Has anyone succeeded in configuring PL by multiple transfers?

 

Would appreciate any help….

 

Regards,

joseph

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Visitor
Visitor
3,390 Views
Registered: ‎10-13-2007

a single transfer from qspi works. my guess is that this must be some bug in the dma transfer - like one extra or less for each transfer. this bug probably is not seen when the transfer is a single one as there are enough padding at the start and end.

 

interesting that none of the xilinx people responded to the problem!

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Visitor
Visitor
3,391 Views
Registered: ‎10-13-2007

a single transfer from qspi works. my guess is that this must be some bug in the dma transfer - like one extra or less for each transfer. this bug probably is not seen when the transfer is a single one as there are enough padding at the start and end.

 

interesting that none of the xilinx people responded to the problem!

View solution in original post

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Visitor
Visitor
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Registered: ‎03-26-2018

Did you ever have success with this? I am wanting to do the exact procedure as described above and am seeing the same problem. I am not able to do the DMA directly out of QSPI because we plan on having the bitstream above the linear address space, so this is our only option. 

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Visitor
Visitor
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Registered: ‎03-26-2018

Was a software related bug where the DMA transfer length is in words and not bytes.

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