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Contributor
Contributor
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Registered: ‎09-05-2018

Zynq SPI slave mode and chip select pin

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Hi all,

I wonder if anyone can confirm the behaviour I have noticed where the slave transmit FIFO does not seem to empty if chip select is not independently asserted for every byte.  This is a relatively slow process and I was hoping to avoid the need to toggle CS for every byte.

If I hold CS continuously low for each transaction it seems only the first transmit byte makes it out of the FIFO;  that byte is endlessly repeated until the next CS window.  I must pull CS high during idle period, then low again when the next byte is ready, to get the FIFO to output correctly.

Is this an option that can be configured?  I am aware of some different behaviour of CS with CPOL and CPHA settings, but haven't found documentation from Xilinx describing these.  I am using standard SPI mode 0 (CPOL=0, CPHA=0).  My device is XC7Z014S, and I am using the SPI peripheral on the PS via EMIO to FPGA pins.

Any input appreciated

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Contributor
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Registered: ‎09-05-2018

Re: Zynq SPI slave mode and chip select pin

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The issue has been resolved.  It was ultimately due to two problems:

- A bug in my interrupt handler

- A defective level shifter IC was causing the double-bit and other bit corruption issues.

View solution in original post

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Contributor
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Registered: ‎09-05-2018

Re: Zynq SPI slave mode and chip select pin

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Further analysis of the problem, I seem to be able to work around this by pushing at least 4 bytes into the TxFIFO before the first interrupt.  Obviously, my transmit output is then shifted by 4 bytes, although I can work around this.  But, it still seems like odd behaviour to me, and could cause problems later on.  Is there a better solution?

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Contributor
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Registered: ‎09-05-2018

Re: Zynq SPI slave mode and chip select pin

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Perhaps someone at Xilinx can explain this particularly odd behaviour of the Cadence core where I am getting data bits clocked on both edges of my SPI clock.  If you look carefully, you can see data is changing on both the rising and falling edges of the clock.  This is a complete violation of the SPI behaviour model.

In this example, CPHA=0 and CPOL=0,  though I'm not sure either have much relevance when the interface is DDR-like!

What on earth is going on?

Dark blue trace is data output from Zynq (MISO);  Yellow is clock.  Dark blue is on FPGA domain (1.8V signalling),  yellow is on 3.3V domain (MCU signalling) but I've verified that there's no substantial difference on the 1.8V side of this. Purple trace is /CS and light blue is MOSI, not used.

Any input appreciated while I tear out what little hair I have...

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Highlighted
Contributor
Contributor
203 Views
Registered: ‎09-05-2018

Re: Zynq SPI slave mode and chip select pin

Jump to solution

The issue has been resolved.  It was ultimately due to two problems:

- A bug in my interrupt handler

- A defective level shifter IC was causing the double-bit and other bit corruption issues.

View solution in original post

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